IS43DR16640A-3DBL INTEGRATED SILICON SOLUTION (ISSI), IS43DR16640A-3DBL Datasheet - Page 18

• Manufacturer Part Number: IS43DR16640A-3DBL
• Description: SDRAM, DDR2, 64M X 16, 1.8V, 84BGA
• Manufacturer: INTEGRATED SILICON SOLUTION (ISSI)

Specifications of IS43DR16640A-3DBL

• Access Time: 0.45ns
• Memory Case Style: BGA
• No. Of Pins: 84
• Memory Type: SDRAM
• Memory Configuration: 8 BLK (8M X 16)
• Page Size: 1GB
• Operating Temperature Range: 0°C To +70°C
• Frequency: 333MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS43/46DR81280A, IS43/46DR16640A
ODT DC Electrical Characteristics
Note:
1.
2.
Notes:
1.
2.
3.
4.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. B, 06/01/2011
ODT AC Electrical Characteristics and Operating Conditions
tAONPD
tAOFPD
Symbol
tAOND
tAOFD
tANPD
tAXPD
tAON
tAOF
Measurement Definition for Rtt(eff):
Apply VIHac and VILac to test pin seperately, then measure current I(VIHac) and I(VILac) respectively
Measurement Defintion for VM:
Measure voltage (VM) at test pin (midpoint) with no load:
ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully
on. Both are measured from tAOND.
ODT turn off time min is when the device starts to turn-off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from
tAOFD.
For Standard Active Power-Down (with MR S A12 = “0”), the non power -down timings (tAOND, tAON, tAOFD and tAOF) apply.
tANPD an d tAXPD define the timing limit when either Power Down Mode Timings (tAONPD, tAOFPD) or Non-Power Down Mode timings (tAOND, tAOFD) have
to be applied
Rtt effective impedance value for EMRS(A6=1, A2=0); 150 ohm
Rtt effective impedance value for EMRS(A6=0, A2=1); 75 ohm
Rtt effective impedance value for EMRS(A6=A2=1); 50 ohm
Parameter/Condition
ODT turn-on delay
ODT turn-on
ODT turn-on (Power-Down Mode)
ODT turn-off delay
ODT turn-off
ODT turn-off (Power-Down Mode)
ODT to Power-Down Mode Entry L:atency
ODT Power Down Exit Latency
Deviation of VM with respect to VDDQ/2
Parameter/Condition
Rtt
∆
(
eff
VM
)
=
=



( I
VIH
2
VDDQ
VIH
x
tAC(Min)+2ns
tAC(Min)+2ns
VM
(
AC
(
tAC(Min)
tAC(Min)
AC
))
−
Min.
)
2.5
−
−
1
2
3
8



( I
VIL
x
VIL
100
(
AC
(
AC
%
Delta VM
Rtt1(eff)
Rtt2(eff)
Rtt3(eff)
)
Symbol
))
2tCK+tAC(Max)+1ns
Min.
120
2.5tCK+tAC+1ns
tAC(Max)+0.7ns
tAC(Max)+0.6ns
60
40
-6
Max.
2.5
2
Nom.
150
75
50
Max.
180
90
60
+6
Units
tCK
tCK
tCK
tCK
ohms
Units
ohms
ohms
ns
ns
ns
ns
%
Notes
Notes
1
1
1
2
1
3
2
3
4
4
18