IS43DR16640A-3DBL INTEGRATED SILICON SOLUTION (ISSI), IS43DR16640A-3DBL Datasheet - Page 24

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IS43DR16640A-3DBL

Manufacturer Part Number
IS43DR16640A-3DBL
Description
SDRAM, DDR2, 64M X 16, 1.8V, 84BGA
Manufacturer
INTEGRATED SILICON SOLUTION (ISSI)
Datasheet

Specifications of IS43DR16640A-3DBL

Access Time
0.45ns
Memory Case Style
BGA
No. Of Pins
84
Memory Type
SDRAM
Memory Configuration
8 BLK (8M X 16)
Page Size
1GB
Operating Temperature Range
0°C To +70°C
Frequency
333MHz
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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IS43/46DR81280A, IS43/46DR16640A
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10. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus
11. A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device. (Note: tRFC depends on DRAM density)
12. For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter
13. Parameter tWTR is at least two clocks independent of operation frequency.
14. User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active power-down mode” (MRS,
15. Timings are guaranteed with command / address input slew rate of 1.0 V/ns.
16. Timings are guaranteed with data / mask input slew rate of 1.0 V/ns.
17. Timings are guaranteed with CK/CK# differential slew rate 2.0 V/ns, and DQS/DQS# (and RDQS/RDQS#) differential slew rate 2.0 V/ns in differential strobe
18. If refresh timing or tDS / tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed.
19. In all circumstances, tXSNR can be satisfied using tXSNR = tRFC + 10 ns.
20. The tRCD timing parameter is valid for both activate command to read or write command with and without Auto-Precharge. Therefore a separate parameter
21.
22. Definitions:
23. Applicable to certain temperature grades. Specified OPER (Tc and Ta) must not be violated for each temperature grade.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. B, 06/01/2011
Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as LOW.
The output timing reference voltage level is VTT.
The values tCL(min) and tCH(min) refer to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be
greater than the minimum specification limits for tCL and tCH.
For input frequency change during DRAM operation.
Transitions for tHZ and tLZ occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but
specify when the device is no longer driving (HZ), or begins driving (LZ).
These parameters guarantee device timing, but they are not necessarily tested on each device.
The specific requirement is that DQS and DQS# be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined
as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning
from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
When programmed in differential strobe mode, DQS is always the logic complement of DQS except when both are in high-Z.
turnaround) degrades accordingly.
stored in the MRS.
A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-down mode” (MRS, A12 = “1”) a slow power-down exit timing tXARDS has to
be satisfied.
mode.
tRAP for activate command to read or write command with Auto-Precharge is not necessary anymore.
tRAS(max) is calculated from the maximum amount of time a DDR2 device can operate without a Refresh command which is equal to 9 x tREFI.
a.
b.
c.
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e.
f.
g.
tCK(avg): tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window.
tCH(avg): tCH(avg) is defined as the average HIGH pulse width, as calculated across any consecutive 200 HIGH pulses.
tCL(avg): tCL(avg) is defined as the average LOW pulse width, as calculated across any consecutive 200 LOW pulses.
tJITDTY: tJITDTY is defined as the cumulative set of tCH jitter and tCL jitter. tCH jitter is the largest deviation of any single tCH from tCH(avg). tCL jitter
is the largest deviation of any single tCL from tCL(avg)
tJITPER: tJITPER is defined as the largest deviation of any single tCK from tCK(avg).
tJITCC: tJITCC is defined as the difference in clock period between two consecutive clock cycles: tJITCC is not guaranteed through final production
testing
tERR: tERR is defined as the cumulative error across multiple consecutive cycles from tCK (avg).
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