IS43DR16640A-3DBL INTEGRATED SILICON SOLUTION (ISSI), IS43DR16640A-3DBL Datasheet - Page 25

• Manufacturer Part Number: IS43DR16640A-3DBL
• Description: SDRAM, DDR2, 64M X 16, 1.8V, 84BGA
• Manufacturer: INTEGRATED SILICON SOLUTION (ISSI)

Specifications of IS43DR16640A-3DBL

• Access Time: 0.45ns
• Memory Case Style: BGA
• No. Of Pins: 84
• Memory Type: SDRAM
• Memory Configuration: 8 BLK (8M X 16)
• Page Size: 1GB
• Operating Temperature Range: 0°C To +70°C
• Frequency: 333MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS43/46DR81280A, IS43/46DR16640A
Reference Loads, Slew Rates and Slew Rate Derating
1. Reference Load for Timing Measurements
Figure AC Timing Reference Load represents the timing reference load used in defining the relevant timing parameters of the part. It
is not intended to be either a precise representation of the typical system environment or a depiction of the actual load presented
by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system
environment. Manufacturers correlate to their production test conditions (generally a coaxial transmission line terminated at the
tester electronics). This load circuit is also used for output slew rate measurements.
AC Timing Reference Load
The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output timing reference voltage
level for differential signals is the crosspoint of the true (e.g. DQS) and the complement (e.g. DQS#) signal.
2. Slew Rate Measurements
a) Output Slew Rate
Output slew rate is characterized under the test conditions as shown in the figure below.
Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for single ended signals. For
differential signals (e.g. DQS – DQS#) output slew rate is measured between DQS – DQS# = - 500 mV and DQS – DQS# = + 500 mV.
Output slew rate is guaranteed by design, but is not necessarily tested on each device.
b) Input Slew Rate
Input slew rate for single ended signals is measured from VREF(DC) to VIH(AC),min for rising edges and from VREF(DC) to VIL(AC),min
for falling edges. For differential signals (e.g. CK – CK#) slew rate for rising edges is measured from CK – CK# = - 250 mV to CK - CK = +
500 mV (+ 250 mV to - 500 mV for falling edges). Test conditions are the same as for timing measurements.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. B, 06/01/2011
CK, CK#
DUT
DUT
VDDQ
Reference
VDDQ
Timing
Points
RDQS#
RDQS
DQS#
RDQS
DQS
DQS
DQ
DQ
Output
Test Point
25•
25•
VTT=VDDQ/2
VTT=VDDQ/2
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