IS43DR16640A-3DBL INTEGRATED SILICON SOLUTION (ISSI), IS43DR16640A-3DBL Datasheet - Page 6

• Manufacturer Part Number: IS43DR16640A-3DBL
• Description: SDRAM, DDR2, 64M X 16, 1.8V, 84BGA
• Manufacturer: INTEGRATED SILICON SOLUTION (ISSI)

Specifications of IS43DR16640A-3DBL

• Access Time: 0.45ns
• Memory Case Style: BGA
• No. Of Pins: 84
• Memory Type: SDRAM
• Memory Configuration: 8 BLK (8M X 16)
• Page Size: 1GB
• Operating Temperature Range: 0°C To +70°C
• Frequency: 333MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IS43/46DR81280A, IS43/46DR16640A
Mode Register (MR) Diagram
Notes:
1.
2.
DDR2 Extended Mode Register 1 (EMR[1]) Setting
The extended mode register 1 stores the data for enabling or disabling the DLL, output driver strength, ODT value selection and
additive latency. The default value of the extended mode register is not defined, therefore the extended mode register must be
written after power-up for proper operation. Extended mode register 1 is written by asserting LOW on CS#, RAS#, CAS#, WE#, BA1,
and BA2, and HIGH on BA0, and controlling pins A0 – A13. The DDR2 SDRAM should be in all bank precharge with CKE already HIGH
prior to writing into the extended mode register. The mode register set command cycle time (tMRD) must be satisfied to complete
the write operation to the extended mode register. Mode register contents can be changed using the same command and clock
cycle requirements during normal operation as long as all banks are in the precharge state. A0 is used for DLL enable or disable. A1 is
used for enabling reduced strength data-output driver. A3 - A5 determines the additive latency, A2 and A6 are used for ODT value
selection, A7 - A9 are used for OCD control, A10 is used for DQS# disable and A11 is used for RDQS enable.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. B, 06/01/2011
A13 is reserved for future use and must be set to 0 when programming the MR.
WR(write recovery for autoprecharge) min is determined by tCK max and WR max is determined by tCK min. WR in clock cycles is calculated by dividing tWR (in
ns) by tCK (in ns) and rounding up a non-integer value to the next integer (WR[cycles] = tWR(ns)/tCK(ns)). The mode register must be programmed to this value.
This is also used with tRP to determine tDAL.
Address
A13
Field
BA2
BA1
BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
(1)
Register
Latency
Length
Mode
Burst
PD1
CAS
WR
DLL
TM
BT
0
0
0
0
A12
A11
A8
A6
A3
A2
0
1
0
0
0
0
1
1
1
1
0
1
0
0
0
0
1
1
1
1
0
1
0
0
A10
Active power down exit time
A5
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
Slow exit(use tXARDS)
Fast exit (use tXARD)
Burst Type
Sequential
Interleave
DLL Reset
Yes
A9
No
A4
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
WR(cycles)
BL
4
8
Reserved
2
3
4
5
6
7
8
CAS Latency
Reserved
Reserved
Reserved
(2)
3
4
5
6
7
A7
0
1
Reserved
Normal
Mode
6