A25L016M-F AMIC, A25L016M-F Datasheet
A25L016M-F
Specifications of A25L016M-F
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A25L016M-F Summary of contents
Page 1
... P30: Change D to Min. (October, 2010, Version 1.4) 16Mbit Low Voltage, Serial Flash Memory With 100MHz Uniform 4KB Sectors for 100MHz to 25μA CC2 A25L016 Series Issue Date Remark April 2, 2008 Final December 26, 2008 April 9, 2009 April 23, 2010 October 27, 2010 AMIC Technology Corp. ...
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... The whole memory can be erased using the Chip Erase instruction, a block at a time, using Block Erase instruction sector at a time, using the Sector Erase instruction. SOP16 Connections A25L016 HOLD DIO Note not Use 1 A25L016 Series DIP8 Connections A25L016 HOLD DIO SS AMIC Technology Corp. ...
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... Read Dual Input-Output instruction. (October, 2010, Version 1.4) High Voltage Generator I/O Shift Register 256 Byte Data Buffer 00000h 256 Byte (Page Size) X Decoder A25L016 Series Status Register 1FFFFF Size of the memory area 000FFh Logic Symbol V CC DIO A25L016 W HOLD V SS AMIC Technology Corp. ...
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... The main purpose of this input signal is Write Protect ( W to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP2, BP1, and BP0 bits of the Status Register). AMIC Technology Corp. 3 A25L016 Series required ) signal is used to pause ...
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... C remains at 0 for (CPOL=0, CPHA=0) – C remains at 1 for (CPOL=1, CPHA= DIO SPI Memory Device S W HOLD HOLD ) signals should be driven, High or Low as appropriate MSB DO 4 A25L016 Series C DO DIO C DO SPI Memory SPI Memory Device Device S W HOLD S MSB AMIC Technology Corp. DIO W HOLD ...
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... Write, Program and Erase instructions, as all instructions are ignored except one particular instruction (the Release from Deep Power-down instruction). 5 A25L016 Series ) signal allow the device to be put in the Hardware PUW W ) signal allows the Block Protect AMIC Technology Corp signal. ) can provide ...
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... A25L016 Series Density Portion None None 64KB Upper 1/32 128KB Upper 1/16 256KB Upper 1/8 512KB Upper 1/4 1MB Upper 1/2 2MB All AMIC Technology Corp. ...
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... To restart communication with the device necessary to drive Hold ( Chip Select ( S ) Low. This prevents the device from going back to the Hold condition. Hold Hold Condition Condition (standard use) (non-standard use) 7 A25L016 Series S ) HOLD ) High, and then to drive AMIC Technology Corp. ...
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... FF000h FFFFFh 240 F0000h F0FFFh 239 EF000h EFFFFh 224 E0000h E0FFFh 223 DF000h DFFFFh 208 D0000h D0FFFh 207 CF000h CFFFFh 192 C0000h C0FFFh 191 BF000h BFFFFh 176 B0000h B0FFFh 175 AF000h AFFFFh 160 A0000h A0FFFh AMIC Technology Corp. ...
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... A25L016 Series Sector Address range 63 3F000h 3FFFFh 48 30000h 30FFFh 47 2F000h 2FFFFh 32 20000h 20FFFh 31 1F000h 1FFFFh 16 10000h 10FFFh 15 0F000h 0FFFFh 4 04000h 04FFFh 3 03000h 03FFFh 2 02000h 02FFFh 1 01000h 01FFFh 0 00000h 00FFFh AMIC Technology Corp. ...
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... One-byte Address Dummy Bytes Bytes 06h 0 04h 0 05h 0 01h 0 03h 3 0Bh 3 3Bh 3 (2) BBh 3 02h 3 20h 3 D8h 3 C7h 0 B9h 0 9Fh 0 (3) 90h 1 0 ABh 0 AMIC Technology Corp must be driven S ) must Data Bytes ∞ ∞ ∞ ∞ ( ∞ 256 ∞ ∞ ∞ ...
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... Write Status Register (WRSR) instruction completion ﹣ Page Program (PP) instruction completion ﹣ Sector Erase (SE) instruction completion ﹣ Block Erase (BE) instruction completion ﹣ Chip Erase (CE) instruction completion Instruction DIO High Impedance DO 11 A25L016 Series S ) Low, sending the instruction code, and then S ) High AMIC Technology Corp. ...
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... Register (SRWD, TB, BP2, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution Status Register Out MSB 12 A25L016 Series W ) signal allow the device to be put in the Status Register Out MSB AMIC Technology Corp signal ...
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... Hardware Protected Mode (HPM). The Write Status Register (WRSR) instruction is not executed once the Hardware Protected Mode (HPM) is entered initiated. While the Instruction 7 High Impedance MSB 13 A25L016 Series Status Register AMIC Technology Corp. ) signal. The Status W ) ...
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... Ready to accept Page Program, Dual Input Fast Program, Sector Erase, and Block Erase instructions Ready to accept Page Program, Dual Input Fast Program, Sector Erase, and Block Erase instructions W ) Low W ) Low after setting the W ) High permanently tied High, the Hardware AMIC Technology Corp. 1 ...
Page 16
... High at any time during data output. Any Read Data Bytes (READ) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress 24-Bit Address MSB 15 A25L016 Series High. Chip Select ( 0 Data Out 2 Data Out MSB . AMIC Technology Corp. ) can be driven ...
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... Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress Instruction 24-Bit Address MSB Data Out MSB 16 A25L016 Series S ) can be driven High at any time during data Data Out MSB . AMIC Technology Corp High. 7 MSB ...
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... However, the DIO pin should be high-impedance prior to the falling edge of the first data out clock. This Instruction 24-Bit Address MSB DIO switches from input to output MSB Data Out 1 Data Out 2 17 A25L016 Series MSB MSB Data Out 3 Data Out 4 . AMIC Technology Corp. ...
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... However, the DIO and DO pins should be high-impedance prior to the falling edge of the first data out clock. This Instruction 24-Bit Address MSB DIO switches from input to output MSB MSB Data Out 2 Data Out 3 Data Out 1 18 A25L016 Series MSB Data Out 4 Data Out 5 . AMIC Technology Corp. 7 MSB ...
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... Block Protect (BP2, BP1, BP0) bits (see table 1 and table 2) is not executed Instruction 24-Bit Address MSB Data Byte MSB 19 A25L016 Series S ) must be driven High after the eighth bit of the driven High, the self-timed Data Byte MSB Data Byte 256 MSB . AMIC Technology Corp initiated. While PP ...
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... Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) instruction applied to a page which is protected by the Block Protect (TB, BP2, BP1, BP0) bits (see table 1 and table 2) is not executed Instruction 24-Bit Address MSB 20 A25L016 Series ) is initiated. While the Sector Erase cycle AMIC Technology Corp ...
Page 22
... Write Enable Latch (WEL) bit is reset. A Block Erase (BE) instruction applied to a page which is protected by the Block Protect (TB, BP2, BP1, BP0) bits (see table 1and table 2) is not executed Instruction MSB 21 A25L016 Series ) is initiated. While the Block Erase cycle is in progress 24-Bit Address AMIC Technology Corp ...
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... At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Chip Erase (CE) instruction is executed only if all Block Protect (TB, BP2, BP1, BP0) bits are 0. The Chip Erase (CE) instruction is ignored if one, or more, blocks are protected Instruction 22 A25L016 Series S . AMIC Technology Corp ...
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... Instruction Stand-by Mode 23 A25L016 Series S ) Low, followed by the instruction code must be driven Low S ) must be driven High after the eighth bit of the driven High, it requires a delay Deep Power-down Mode AMIC Technology Corp. DP and the Deep CC2 ...
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... S and execute instructions. ) Low. Device Identification Memory Type 30h Manufacture ID Memory Type 24 A25L016 Series S ) High at any time during data output driven High, the device is put in the Memory Capacity 15h Memory Capacity AMIC Technology Corp. ...
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... The manufacturer identification is assigned by JEDEC, and has the value 37h for AMIC. The device identification is assigned by the device manufacturer, and has the value 15h for A25L032, 14h for A25L016. ...
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... Note: The value of the 8-bit Electronic Signature is 14h. 26 A25L016 Series S ) High after the Electronic Signature has been read driven Low, cause the driven High, the device is put in the , and Chip Select ( RES2 (max), as specified in AC RES2 t RES2 AMIC Technology Corp Stand-by Mode ...
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... Stand-by Power mode is delayed by t and Chip Select ( as specified in AC Characteristics Table. Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. 27 A25L016 Series RES1 Stand-by Mode S ) must remain High for at least t AMIC Technology Corp. , RES1 (max), RES1 ...
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... The device is in the Standby mode (not the Deep Power-down mode). The Write Enable Latch (WEL) bit is reset. feed. Each device in a system should CC rail decoupled by a suitable capacitor close to CC drops from the operating voltage, CC Full Device Access time AMIC Technology Corp. has risen above CC , all operations are WI ...
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... INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). (October, 2010, Version 1.4) Parameter 29 A25L016 Series Min. Max. Unit 2 AMIC Technology Corp. ...
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... Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the AMIC SURE Program and other relevant quality docu- ments. Measurement Conditions summarized in the relevant tables. Designers should check that the operating conditions in their ...
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... DO = open 1.6mA –100µA OH Parameter Parameter 31 A25L016 Series Min. Max –0.5 0.3V 0. –0.2 CC Min. Typ. Max 0.2 0.24 0.5 1 Min. Max 0. 0. AMIC Technology Corp. Unit ± 2 µA ± 2 µA 25 µA 25 µ +0 Unit Unit ...
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... Figure 22. AC Measurement I/O Waveform 0.8V 0.2V (October, 2010, Version 1.4) Input Levels A25L016 Series Input and Output Timing Reference Levels 0.7V CC 0.5V CC 0.3V CC AMIC Technology Corp. ...
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... Only applicable as a constraint for a WRSR instruction when SRWD is set at 1. (October, 2010, Version 1.4) Parameter 3 (peak to peak) 3 (peak to peak A25L016 Series Min. Typ. Max. Unit D.C. 100 MHz D.C. 50 MHz 0.1 V/ns 0.1 V/ 100 100 ns 3 µs 30 µs 30 µ 0.2 0.24 s 0.5 1 AMIC Technology Corp. ...
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... Figure 23. Serial Input Timing S tCHSL C tDVCH DIO DO Figure 24. Write Protect Setup and Hold Timing during WRSR when SRWD=1 W tWHSL S C DIO DO (October, 2010, Version 1.4) tSLCH tCHDX MSB IN High Impedance High Impedance 34 A25L016 Series tSHSL tSHCH tCHSH tCHCL tCLCH LSB IN tSHWL AMIC Technology Corp. ...
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... Hold Timing Figure 25 DIO DO HOLD Figure 26. Output Timing S C DIO ADDR.LSB IN tCLQV tCLQX tCLQX DO (October, 2010, Version 1.4) tHLCH tCHHL tCHHH tHLQZ tCH tCLQV 35 A25L016 Series tHHCH tHHQX tCL LSB OUT tQLQH tQHQL AMIC Technology Corp. tSHQZ ...
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... Mbit (4KB uniform sectors) 020 = 2 Mbit (4KB uniform sectors) 040 = 4 Mbit (4KB uniform sectors) 080 = 8 Mbit (4KB uniform sectors) 016 = 16 Mbit (4KB uniform sectors) 032 = 32 Mbit (4KB uniform sectors) Device Voltage L = 2.7-3.6V Device Type A25 = AMIC Serial Flash AMIC Technology Corp. ...
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... Ordering Information Part No. Speed (MHz) A25L016-F A25L016-UF A25L016M-F 100 A25L016M-UF A25L016N-F A25L016N-UF Blank is for commercial operating temperature range: 0 ° +70 ° for industrial operating temperature range: -40°C ~ +85°C (October, 2010, Version 1.4) Active Read Program/Erase Current Current Max. (mA) Max. (mA A25L016 Series Standby Current Package Max. (μ ...
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... Dimensions in mm Min Nom Max - - 4.57 0. 3.25 3.30 3.45 0.36 0.46 0.56 1.27 1.52 1.78 0.81 0.99 1.17 0.20 0.25 0.33 8.89 9.14 9.40 7.37 7.62 8.00 6.45 6.60 6.76 - 2. 8.76 - 9.78 0.41 0.53 0.66 AMIC Technology Corp. unit: inches/mm ...
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... E 7.70 7.90 E 5.18 5. 1.27 BSC L 0.50 0.65 θ 0° - Notes: Maximum allowable mold flash is 0.15mm at the package ends and 0.25mm between leads 39 A25L016 Series unit θ L Max 2.16 0.25 1.91 0.48 0.25 5.33 8.10 5.38 0.80 8° AMIC Technology Corp. ...
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... L 0.016 0.050 θ 8° 0° gate burrs. 40 A25L016 Series unit: inches/ θ L Dimensions in mm Min Max 2.36 2.65 0.10 0.30 0.41 Typ. 0.20 Typ. 10.10 10.50 7.39 7.60 1.27 Typ. 10.01 10.64 0.40 1.27 8° 0° AMIC Technology Corp. ...