S25FL016K0XMFI011 Spansion Inc., S25FL016K0XMFI011 Datasheet
S25FL016K0XMFI011
Specifications of S25FL016K0XMFI011
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S25FL016K0XMFI011 Summary of contents
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S25FL016K 16-Mbit CMOS 3.0 Volt Flash Memory with 104-MHz SPI (Serial Peripheral Interface) Multi I/O Bus Data Sheet (Preliminary) Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may ...
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... Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.” ...
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S25FL016K 16-Mbit CMOS 3.0 Volt Flash Memory with 104-MHz SPI (Serial Peripheral Interface) Multi I/O Bus Data Sheet (Preliminary) Distinctive Characteristics Architectural Advantages Single power supply operation – Full voltage range: 2.7 to 3.6V read and write operations ...
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General Description The S25FL016K (16-Mbit) Serial Flash memory provides an ideal storage solution for systems with limited space, pins and power. The device offers flexibility and performance well beyond ordinary Serial Flash devices ideal for code shadowing to ...
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Table of Contents Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figures Figure 2.1 8-pin Plastic Small Outline Package (SO ...
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Tables Table 3.1 8-pin SOIC 150-mil / 208-mil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Block Diagram 000000h 000000h Block Segmentation Block Segmentation xxFF00h xxFF00h • xxF000h xxF000h xxEF00h xxEF00h • xxE000h xxE000h xxDF00h xxDF00h • xxD000h xxD000h xx2F00h xx2F00h • xx2000h xx2000h xx1F00h xx1F00h • xx1000h xx1000h xx0F00h xx0F00h ...
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Connection Diagrams 3. Input/Output Descriptions Pin No Notes: 1. IO0 and IO1 are used for Standard and Dual SPI instructions. 2. IO0 – IO3 are used for Quad SPI instructions. 10 ...
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Ordering Information The ordering part number is formed by a valid combination of the following: S25FL 016 K 4.1 Valid Combinations Table 4.1 lists the valid combinations configurations planned to be supported in volume for ...
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Functional Description 5.1 SPI Operations 5.1.1 Standard SPI Instructions The S25FL016K is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK), Chip Select (CS#), Serial Data Input (SI) and Serial Data Output (SO). Standard SPI ...
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5.2.1 Write Protect Features Device resets when V Time delay write disable after Power-up Write enable/disable instructions and automatic write disable after erase or program Software and Hardware (WP# pin) write protection ...
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Status Register 6.1.1 BUSY BUSY is a read only bit in the status register (S0) that is set state when the device is executing a Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, ...
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SRP1 SRP0 Notes: 1. When SRP1, SRP0 = (1, 0), a power-down, power-up cycle will change SRP1, SRP0 to (0, 0) state. 2. This feature is ...
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Status Register SEC TB BP2 ...
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Status Register SEC TB BP2 ...
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Instructions The instruction set of the S25FL016K consists of thirty five basic instructions that are fully controlled through the SPI bus (see Table 7.3 Select (CS#). The first byte of data clocked into the SI input provides the instruction ...
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Instruction Name Read Data Fast Read Fast Read Dual Output Fast Read Quad Output Fast Read Dual I/O Fast Read Quad I/O Word Read Quad I/O (7) Octal Word Read Quad I/O Set Burst with Wrap ...
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Instruction Name Release from Deep Power down / Device ID Manufacturer/ Device ID Manufacturer/Device ID by Dual I/O Manufacture/Device ID by Quad I/O JEDEC ID Read Unique ID Read SFDP Register Erase Security Registers Program Security Registers Read Security Registers ...
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7.2 Write Enable for Volatile Status Register (50h) The non-volatile Status Register bits described volatile bits. This gives more flexibility to change the system configuration and memory protection schemes quickly without waiting for ...
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Read Status Register-1 (05h) and Read Status Register-2 (35h) The Read Status Register instructions allow the 8-bit Status Registers to be read. The instruction is entered by driving CS# low and shifting the instruction code “05h” for Status Register-1 ...
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During volatile Status Register write operation (50h combined with 01h), after CS# is driven high, the Status Register bits will be refreshed to the new values within the time period of t Electrical Characteristics on page ...
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Fast Read (0Bh) The Fast Read instruction is similar to the Read Data instruction except that it can operate at the highest possible frequency of F adding eight “dummy” clocks after the 24-bit address as shown in devices internal ...
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7.8 Fast Read Dual Output (3Bh) The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction except that data is output on two pins; IO0 and IO1. This allows data ...
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Fast Read Quad Output (6Bh) The Fast Read Quad Output (6Bh) instruction is similar to the Fast Read Dual Output (3Bh) instruction except that data is output on four pins, IO0, IO1, IO2, and IO3. A Quad enable of ...
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7.10 Fast Read Dual I/O (BBh) The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO pins, IO0 and IO1 similar to the Fast Read Dual Output (3Bh) ...
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Figure 7.11 Fast Read Dual I/O Instruction Sequence (Previous instruction set M5-4 = 10) CS# Mode 3 CLK Mode 0 IO0 6 IO1 7 CS CLK IO0 IO1 Byte ...
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7.11 Fast Read Quad I/O (EBh) The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except that address and data bits are input and output through four pins ...
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Figure 7.13 Fast Read Quad I/O Instruction Sequence (Previous instruction set M5-4 = 10) CS# Mode 3 0 CLK Mode 0 4 IO0 IO1 5 IO2 6 IO3 7 A23-16 Fast Read Quad I/O with “8/16/32/64-Byte Wrap Around” The Fast ...
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7.12 Word Read Quad I/O (E7h) The Word Read Quad I/O (E7h) instruction is similar to the Fast Read Quad I/O (EBh) instruction except that the lowest Address bit (A0) must equal 0 and only two ...
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Figure 7.15 Word Read Quad I/O Instruction Sequence (Previous instruction set M5-4 = 10) CS# Mode 3 Mode 0 CLK IO0 IO1 IO2 IO3 Word Read Quad I/O with “8/16/32/64-Byte Wrap Around” The Word Read Quad I/O instruction can also ...
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7.13 Octal Word Read Quad I/O (E3h) The Octal Word Read Quad I/O (E3h) instruction is similar to the Fast Read Quad I/O (EBh) instruction except that the lower four Address bits (A0, A1, A2, A3) ...
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Figure 7.17 Octal Word Read Quad I/O Instruction Sequence (Previous instruction set M5-4 = 10) CS# Mode 3 CLK Mode 0 IO0 IO1 IO2 IO3 ...
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7.14 Set Burst with Wrap (77h) The Set Burst with Wrap (77h) instruction is used in conjunction with “Fast Read Quad I/O” and “Word Read Quad I/O” instructions to access a fixed length of 8/16/32/64-byte section ...
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Continuous Read Mode Bits (M7-0) The “Continuous Read Mode” bits are used in conjunction with “Fast Read Dual I/O”, “Fast Read Quad I/O”, “Word Read Quad I/O” and “Octal Word Read Quad I/O” instructions to provide the highest random ...
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7.17 Page Program (02h) The Page Program instruction allows from one byte to 256 bytes (a page) of data to be programmed at previously erased (FFh) memory locations. A Write Enable instruction must be executed before ...
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Quad Page Program (32h) The Quad Page Program instruction allows up to 256 bytes of data to be programmed at previously erased (FFh) memory locations using four pins: IO0, IO1, IO2, and IO3. The Quad Page Program can improve ...
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7.19 Sector Erase (20h) The Sector Erase instruction sets all memory within a specified sector (4K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept ...
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KB Block Erase (52h) The Block Erase instruction sets all memory within a specified block (32K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block ...
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7. Block Erase (D8h) The Block Erase instruction sets all memory within a specified block (64K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device ...
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Chip Erase (C7h / 60h) The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Chip Erase Instruction ...
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7.23 Erase / Program Suspend (75h) The Erase/Program Suspend instruction “75h”, allows the system to interrupt a Sector or Block Erase operation or a Page Program operation and then read from or program/erase data to, any ...
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Erase / Program Resume (7Ah) The Erase/Program Resume instruction “7Ah” must be written to resume the Sector or Block Erase operation or the Page Program operation after an Erase/Program Suspend. The Resume instruction “7Ah” will be accepted by the ...
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7.25 Deep Power-down (B9h) Although the standby current during normal operation is relatively low, standby current can be further reduced with the Deep Power-down instruction. The lower power consumption makes the Deep Power-down instruction especially useful ...
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Release from Deep Power-down / Device ID (ABh) The Release from Deep Power-down / Device ID instruction is a multi-purpose instruction. It can be used to release the device from the deep power-down state, or obtain the devices electronic ...
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7.27 Read Manufacturer / Device ID (90h) The Read Manufacturer/Device ID instruction is an alternative to the Release from Deep Power-down / Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific ...
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Read Manufacturer / Device ID Dual I/O (92h) The Read Manufacturer / Device ID Dual I/O instruction is an alternative to the Read Manufacturer / Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific ...
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7.29 Read Manufacturer / Device ID Quad I/O (94h) The Read Manufacturer / Device ID Quad I/O instruction is an alternative to the Read Manufacturer / Device ID instruction that provides both the JEDEC assigned manufacturer ...
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Read Unique ID Number (4Bh) The Read Unique ID Number instruction accesses a factory-set read-only 64-bit number that is unique to each S25FL016K device. The ID number can be used in conjunction with user software methods to help prevent ...
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7.31 Read JEDEC ID (9Fh) For compatibility reasons, the S25FL016K provides several instructions to electronically determine the identity of the device. The Read JEDEC ID instruction is compatible with the JEDEC standard for SPI compatible serial ...
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Read SFDP Register (5Ah) The S25FL016K features a 256-Byte Serial Flash Discoverable Parameter (SFDP) register that contains information about devices operational capability such as available commands, timing and other features. The SFDP parameters are stored in one or more ...
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Table 7.6 Serial Flash Discoverable Parameter Definition Table (Sheet Byte Address 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h ... (1) 80h 81h 82h 83h 84h ...
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Erase Security Registers (44h) The S25FL016K offers three 256-byte Security Registers which can be erased and programmed individually. These registers may be used by the system manufacturers to store security and other important information separately from the main memory ...
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7.34 Program Security Registers (42h) The Program Security Register instruction is similar to the Page Program instruction. It allows from one byte to 256 bytes of security register data to be programmed at previously erased (FFh) ...
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Read Security Registers (48h) The Read Security Register instruction is similar to the Fast Read instruction and allows one or more data bytes to be sequentially read from one of the three security registers. The instruction is initiated by ...
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Electrical Characteristics Specification for S25FL016K is preliminary. See preliminary designation at the end of this document. 8.1 Absolute Maximum Ratings Parameters Supply Voltage Voltage Applied to Any Pin Transient Voltage on any Pin Storage Temperature ...
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VCC VCC (max) VCC (min) VWI 8.4 DC Electrical Characteristics Parameter Input Capacitance Output Capacitance Input Leakage I/O Leakage Standby Current Deep Power-down Current Current: Read Data / Dual /Quad 1 MHz Current: Read Data / Dual /Quad 33 MHz ...
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8.5 AC Measurement Conditions Parameter Load Capacitance Input Rise and Fall Times Input Pulse Voltages Input Timing Reference Voltages Output Timing Reference Voltages Note: 1. Output Hi-Z is defined as the point where data out is ...
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Description HOLD# Active Setup Time relative to CLK HOLD# Active Hold Time relative to CLK HOLD# Not Active Setup Time relative to CLK HOLD# Not Active Hold Time relative to CLK HOLD# to Output Low-Z HOLD# to Output High-Z Write ...
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8.8 Serial Input Timing CS# t CHSL CLK SIO SO 8.9 Hold Timing CS# CLK SO SIO HOLD# September 8, 2010 S25FL016K_00_02 ...
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Physical Dimensions 9.1 SOA008 narrow — 8-pin Plastic Small Outline Package (150-mils Body Width E1/2 INDEX AREA e (0.25D x 0.75E PACKAGE SOA 008 (inches) ...
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9.2 SOC008 wide — 8-pin Plastic Small Outline Package (208-mils Body Width E1 PACKAGE SOC 008 (inches) SOC 008 (mm) JEDEC SYMBOL ...
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Revision History Section Revision 01 (June 3, 2010) Initial release Revision 02 (September 8, 2010) Global Changed data sheet designation from Advanced Information to Preliminary Block Diagram Updated block diagram Changed heading level Instructions Updated Instruction Set Table to ...
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... Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2010 Spansion Inc. All rights reserved. Spansion and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners ...