S25FL016K0XMFI011 Spansion Inc., S25FL016K0XMFI011 Datasheet - Page 18

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S25FL016K0XMFI011

Manufacturer Part Number
S25FL016K0XMFI011
Description
MEMORY, FLASH, 16M, 3V, SPI, 8SOIC
Manufacturer
Spansion Inc.
Datasheet

Specifications of S25FL016K0XMFI011

Memory Size
16Mbit
Clock Frequency
104MHz
Supply Voltage Range
2.7V To 3.6V
Memory Case Style
SO
No. Of Pins
8
Operating Temperature Range
-40°C To +85°C
Interface
SPI
Memory Type
RoHS Compliant
Memory Configuration
8K X 256 Bytes
Interface Type
SPI
Rohs Compliant
Yes

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
S25FL016K0XMFI011
Manufacturer:
SPANSION
Quantity:
20 000
7.
18
Instructions
The instruction set of the S25FL016K consists of thirty five basic instructions that are fully controlled through
the SPI bus (see
Select (CS#). The first byte of data clocked into the SI input provides the instruction code. Data on the SI
input is sampled on the rising edge of clock with most significant bit (MSB) first.
Instructions vary in length from a single byte to several bytes and may be followed by address bytes, data
bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed with the
rising edge of edge CS#. Clock relative timing diagrams for each instruction are included in the figures below.
All read instructions can be completed after any clocked bit. However, all instructions that Write, Program or
Erase must complete on a byte boundary (CS# driven high after a full 8-bits have been clocked) otherwise the
instruction will be ignored. This feature further protects the device from inadvertent writes. Additionally, while
the memory is being programmed or erased, or when the Status Register is being written, all instructions
except for Read Status Register will be ignored until the program or erase cycle has completed.
Notes:
1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “()” indicate data being read from the device on
2. The Status Register contents will repeat continuously until CS# terminates the instruction.
3. Quad Page Program Input Data: IO0 = (D4, D0, ……) IO1 = (D5, D1, ……) IO2 = (D6, D2, ……) IO3 = (D7, D3, ……)
4. This instruction is recommended when using the Dual or Quad “Continuous Read Mode” feature. See
Write Enable
Write Enable for Volatile Status
Register
Write Disable
Read Status Register-1
Read Status Register-2
Write Status Register
Page Program
Quad Page Program
Sector Erase (4 KB)
Block Erase (32 KB)
Block Erase (64 KB)
Chip Erase
Erase / Program Suspend
Erase / Program Resume
Deep Power-down
Continuous Read Mode Reset
(4)
the SO pin.
on page 36
Instruction Name
for more information.
(ID15-ID0)
Device ID
(ID7-ID0)
Table 7.3
Manufacturer ID
(MF7-MF0)
Table 7.3 Instruction Set (Erase, Program Instructions
to
Table 7.5 on page
C7h/60h
BYTE 1
(CODE)
D a t a
D8h
7Ah
B9h
FFh
06h
50h
04h
05h
35h
01h
02h
32h
20h
52h
75h
Table 7.1 Manufacturer Identification
Table 7.2 Device Identification
S25FL016K
S h e e t
(S15–S8)
(S7–S0)
A23–A16
A23–A16
A23–A16
A23–A16
A23–A16
(S7–S0)
BYTE 2
FFh
20). Instructions are initiated with the falling edge of Chip
Instruction
(2)
(2)
ABh, 90h
9Fh
( P r e l i m i n a r y )
(S15–S8)
A15–A8
A15–A8
A15–A8
A15–A8
A15–A8
BYTE 3
BYTE 4
S25FL016K_00_02 September 8, 2010
A7–A0
A7–A0
A7–A0
A7–A0
A7–A0
Value
EFh
(1))
Section 7.15
(D7–D0, …)
(D7–D0)
BYTE 5
4015h
Value
14h
(3)
and
Section 7.16
BYTE 6

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