S25FL016K0XMFI011 Spansion Inc., S25FL016K0XMFI011 Datasheet - Page 29

• Manufacturer Part Number: S25FL016K0XMFI011
• Description: MEMORY, FLASH, 16M, 3V, SPI, 8SOIC
• Manufacturer: Spansion Inc.

Specifications of S25FL016K0XMFI011

• Memory Size: 16Mbit
• Clock Frequency: 104MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: SO
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Interface: SPI
• Memory Type: RoHS Compliant
• Memory Configuration: 8K X 256 Bytes
• Interface Type: SPI
• Rohs Compliant: Yes

7.11
September 8, 2010 S25FL016K_00_02
Fast Read Quad I/O (EBh)
The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except that
address and data bits are input and output through four pins IO0, IO1, IO2 and IO3 and four Dummy clock are
required prior to the data output. The Quad I/O dramatically reduces instruction overhead allowing faster
random access for code execution (XIP) directly from the Quad SPI. The Quad Enable bit (QE) of Status
Register-2 must be set to enable the Fast Read Quad I/O Instruction.
Fast Read Quad I/O with “Continuous Read Mode”
The Fast Read Quad I/O instruction can further reduce instruction overhead through setting the “Continuous
Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in
Instruction Sequence (Initial instruction or previous M5-4
controls the length of the next Fast Read Quad I/O instruction through the inclusion or exclusion of the first
byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However, the IO pins should be
high-impedance prior to the falling edge of the first data out clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after CS# is
raised and then lowered) does not require the EBh instruction code, as shown in
Quad I/O Instruction Sequence (Previous instruction set M5-4 = 10) on page
sequence by eight clocks and allows the Read address to be immediately entered after CS# is asserted low.
If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction (after CS# is raised and
then lowered) requires the first byte instruction code, thus returning to normal operation. A “Continuous Read
Mode” Reset instruction can also be used to reset (M7-0) before issuing normal instructions (see
Section 7.16, Continuous Read Mode Reset (FFh or FFFFh) on page
CLK
CS#
IO3
IO1
IO2
IO0
Mode 3
Mode 0
Figure 7.12 Fast Read Quad I/O Instruction Sequence (Initial instruction or previous M5-4 10)
D a t a
0
1
Instruction (EBh)
S h e e t
2
3
4
5
( P r e l i m i n a r y )
6
S25FL016K
7
A23-16
4
6
7
5
8
3
0
1
2
9
7
4
5
6
10
A15-8
3
0
1
2
11 12 13

4
6
7
5
10) on page
A7-0
0
2
3
1
4
6
7
5
14 15 16
M7-0
3
0
1
2
36).
29. The upper nibble of the (M7-4)
Dummy Dummy
Figure 7.12, Fast Read Quad I/O
17 18 19 20 21 22 23
30. This reduces the instruction
Figure 7.13, Fast Read
7
4
6
5
Byte 1
0
2
3
1
IO Switches from
Input to Output
4
6
5
Byte 2
7
0
2
3
1
4
5
6
7
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