S25FL016K0XMFI011 Spansion Inc., S25FL016K0XMFI011 Datasheet - Page 33

• Manufacturer Part Number: S25FL016K0XMFI011
• Description: MEMORY, FLASH, 16M, 3V, SPI, 8SOIC
• Manufacturer: Spansion Inc.

Specifications of S25FL016K0XMFI011

• Memory Size: 16Mbit
• Clock Frequency: 104MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: SO
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Interface: SPI
• Memory Type: RoHS Compliant
• Memory Configuration: 8K X 256 Bytes
• Interface Type: SPI
• Rohs Compliant: Yes

7.13
September 8, 2010 S25FL016K_00_02
Octal Word Read Quad I/O (E3h)
The Octal Word Read Quad I/O (E3h) instruction is similar to the Fast Read Quad I/O (EBh) instruction
except that the lower four Address bits (A0, A1, A2, A3) must equal 0. As a result, the dummy clocks are not
required, which further reduces the instruction overhead allowing even faster random access for code
execution (XIP). The Quad Enable bit (QE) of Status Register-2 must be set to enable the Octal Word Read
Quad I/O Instruction.
Octal Word Read Quad I/O with “Continuous Read Mode”
The Octal Word Read Quad I/O instruction can further reduce instruction overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in
Word Read Quad I/O Instruction Sequence (Initial instruction or previous M5-4
nibble of the (M7-4) controls the length of the next Octal Word Read Quad I/O instruction through the
inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”).
However, the IO pins should be high-impedance prior to the falling edge of the first data out clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after CS# is
raised and then lowered) does not require the E3h instruction code, as shown in
Read Quad I/O Instruction Sequence (Previous instruction set M5-4 = 10) on page
instruction sequence by eight clocks and allows the Read address to be immediately entered after CS# is
asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction (after CS# is
raised and then lowered) requires the first byte instruction code, thus returning to normal operation. A
“Continuous Read Mode” Reset instruction can also be used to reset (M7-0) before issuing normal
instructions (see
CS#
CLK
IO3
IO1
IO2
IO0
Figure 7.16 Octal Word Read Quad I/O Instruction Sequence (Initial instruction or previous M5-4  10)
Mode 3
Mode 0
D a t a
0
Section 7.16, Continuous Read Mode Reset (FFh or FFFFh) on page
1
Instruction (E3h)
S h e e t
2
3
4
5
( P r e l i m i n a r y )
6
S25FL016K
7
A23-16
5
6
7
4
8
1
2
3
0
9
5
4
6
A15-8
7
10 11
2
1
3
0
4
6
7
5
A7-0
12 13 14 15
0
2
3
1
4
6
7
5
M7-0
2
3
0
1
5
4
6
Dummy
7
16 17 18 19
0
2
3
1

IO Switches from Input to Output
4
5
6
Byte 1
7
Figure 7.17, Octal Word
10) on page
34. This reduces the
1
2
0
3
Figure 7.16, Octal
36).
5
4
6
7
Byte 2
20 21 22 23
1
2
0
3
33. The upper
4
5
7
Byte 3
6
1
0
3
2
5
6
7
4
33