S25FL016K0XMFI011 Spansion Inc., S25FL016K0XMFI011 Datasheet - Page 37

• Manufacturer Part Number: S25FL016K0XMFI011
• Description: MEMORY, FLASH, 16M, 3V, SPI, 8SOIC
• Manufacturer: Spansion Inc.

Specifications of S25FL016K0XMFI011

• Memory Size: 16Mbit
• Clock Frequency: 104MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: SO
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Interface: SPI
• Memory Type: RoHS Compliant
• Memory Configuration: 8K X 256 Bytes
• Interface Type: SPI
• Rohs Compliant: Yes

7.17
September 8, 2010 S25FL016K_00_02
Page Program (02h)
The Page Program instruction allows from one byte to 256 bytes (a page) of data to be programmed at
previously erased (FFh) memory locations. A Write Enable instruction must be executed before the device
will accept the Page Program Instruction (Status Register bit WEL= 1). The instruction is initiated by driving
the CS# pin low then shifting the instruction code “02h” followed by a 24-bit address (A23-A0) and at least
one data byte, into the SI pin. The CS# pin must be held low for the entire length of the instruction while data
is being sent to the device. The Page Program instruction sequence is shown in
Instruction Sequence Diagram on page
If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address bits)
should be set to 0. If the last address byte is not zero, and the number of clocks exceed the remaining page
length, the addressing will wrap to the beginning of the page. In some cases, less than 256 bytes (a partial
page) can be programmed without having any effect on other bytes within the same page. One condition to
perform a partial page program is that the number of clocks can not exceed the remaining page length. If
more than 256 bytes are sent to the device the addressing will wrap to the beginning of the page and
overwrite previously sent data.
As with the write and erase instructions, the CS# pin must be driven high after the eighth bit of the last byte
has been latched. If this is not done the Page Program instruction will not be executed. After CS# is driven
high, the self-timed Page Program instruction will commence for a time duration of t
Characteristics on page
instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Page
Program cycle and becomes a 0 when the cycle is finished and the device is ready to accept other
instructions again. After the Page Program cycle has finished the Write Enable Latch (WEL) bit in the Status
Register is cleared to 0. The Page Program instruction will not be executed if the addressed page is protected
by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits.
CLK
CLK
CS#
CS#
SI
SI
= MSB
Mode 3
Mode 0
D a t a
7
6
0
S h e e t
5
1
59.). While the Page Program cycle is in progress, the Read Status Register
Figure 7.20 Page Program Instruction Sequence Diagram
4
Instruction (02h)
2
3
3
2
( P r e l i m i n a r y )
4
1
5
S25FL016K
37.
0
6
7
7
6
23
8
5
22 21
9
24-Bit Address
4
10
3
3
28 29
2
2
1
1
30
0
0
31 32 33
7
7
6
6
Figure 7.20, Page Program
5
Data Byte 1
5
PP
34 35 36 37 38 39
4
(See AC Electrical
4
3
3
2
2
1
1
0
0
37