S25FL016K0XMFI011 Spansion Inc., S25FL016K0XMFI011 Datasheet - Page 38

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S25FL016K0XMFI011

Manufacturer Part Number
S25FL016K0XMFI011
Description
MEMORY, FLASH, 16M, 3V, SPI, 8SOIC
Manufacturer
Spansion Inc.
Datasheet

Specifications of S25FL016K0XMFI011

Memory Size
16Mbit
Clock Frequency
104MHz
Supply Voltage Range
2.7V To 3.6V
Memory Case Style
SO
No. Of Pins
8
Operating Temperature Range
-40°C To +85°C
Interface
SPI
Memory Type
RoHS Compliant
Memory Configuration
8K X 256 Bytes
Interface Type
SPI
Rohs Compliant
Yes

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
S25FL016K0XMFI011
Manufacturer:
SPANSION
Quantity:
20 000
7.18
38
Quad Page Program (32h)
The Quad Page Program instruction allows up to 256 bytes of data to be programmed at previously erased
(FFh) memory locations using four pins: IO0, IO1, IO2, and IO3. The Quad Page Program can improve
performance for PROM Programmer and applications that have slow clock speeds <5 MHz. Systems with
faster clock speed will not realize much benefit for the Quad Page Program instruction since the inherent
page program time is much greater than the time it take to clock-in the data.
To use Quad Page Program the Quad Enable in Status Register-2 must be set (QE=1). A Write Enable
instruction must be executed before the device will accept the Quad Page Program instruction (Status
Register-1, WEL=1). The instruction is initiated by driving the CS# pin low then shifting the instruction code
“32h” followed by a 24-bit address (A23-A0) and at least one data byte, into the IO pins. The CS# pin must be
held low for the entire length of the instruction while data is being sent to the device. All other functions of
Quad Page Program are identical to standard Page Program. The Quad Page Program instruction sequence
is shown in
CLK
CLK
IO3
CS#
IO0
IO2
CS#
IO3
IO0
IO2
IO1
IO1
= MSB
Mode 3
Mode 0
Figure 7.21, Quad Page Program Instruction Sequence Diagram on page
40
Byte 5
5
6
7
4
1
2
3
0
41 42 43
0
5
6
7
4
Byte 6
Figure 7.21 Quad Page Program Instruction Sequence Diagram
1
1
2
3
0
Instruction (32h)
2
5
6
7
Byte 7
44
4
3
2
D a t a
1
3
0
45 46 47
4
5
6
7
Byte 8 Byte 9
4
5
1
2
3
0
S25FL016K
6
S h e e t
4
5
6
7
48 49
7
1
2
0
3
23
8
Byte 10 Byte 11 Byte 12
5
6
4
7
22
50
9
0
1
2
24-Bit Address
3
( P r e l i m i n a r y )
21
51 52 53
10
5
6
7
4
2
3
1
28 29
0
3
5
6
4
2
7
54 55
1
2
1
3
30
0
0
S25FL016K_00_02 September 8, 2010
31 32 33
Byte 253 Byte 254 Byte 255 Byte 256
4
5
6
7
Byte 1
4
5
7
6
0
1
2
3
0
1
3
2
4
5
6
7
Byte 2
4
5
7
6
34 35 36 37 38 39
0
1
2
3
0
1
38.
3
2
5
6
4
7
Byte 3
5
7
4
6
2
0
1
3
0
2
1
3
4
5
6
7
Byte 4
4
5
6
7
1
2
0
3
1
3
0
2
Mode 3
Mode 0

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