S25FL016K0XMFI011 Spansion Inc., S25FL016K0XMFI011 Datasheet - Page 42

no-image

S25FL016K0XMFI011

Manufacturer Part Number
S25FL016K0XMFI011
Description
MEMORY, FLASH, 16M, 3V, SPI, 8SOIC
Manufacturer
Spansion Inc.
Datasheet

Specifications of S25FL016K0XMFI011

Memory Size
16Mbit
Clock Frequency
104MHz
Supply Voltage Range
2.7V To 3.6V
Memory Case Style
SO
No. Of Pins
8
Operating Temperature Range
-40°C To +85°C
Interface
SPI
Memory Type
RoHS Compliant
Memory Configuration
8K X 256 Bytes
Interface Type
SPI
Rohs Compliant
Yes

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
S25FL016K0XMFI011
Manufacturer:
SPANSION
Quantity:
20 000
7.22
42
Chip Erase (C7h / 60h)
The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write
Enable instruction must be executed before the device will accept the Chip Erase Instruction (Status Register
bit WEL must equal 1). The instruction is initiated by driving the CS# pin low and shifting the instruction code
“C7h” or “60h”. The Chip Erase instruction sequence is shown in
The CS# pin must be driven high after the eighth bit has been latched. If this is not done the Chip Erase
instruction will not be executed. After CS# is driven high, the self-timed Chip Erase instruction will commence
for a time duration of t
progress, the Read Status Register instruction may still be accessed to check the status of the BUSY bit. The
BUSY bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and the device is ready to accept
other instructions again. After the Chip Erase cycle has finished the Write Enable Latch (WEL) bit in the
Status Register is cleared to 0. The Chip Erase instruction will not be executed if any page is protected by the
Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits (see
(CMP = 0) on page
16).
CLK
CS#
SO
SI
CE
(See AC Electrical Characteristics on page
Figure 7.25 Chip Erase Instruction Sequence Diagram
Mode 3
Mode 0
D a t a
S25FL016K
0
S h e e t
1
Instruction (C7h/60h)
High Impedance
2
( P r e l i m i n a r y )
3
4
Table 6.2, Status Register Memory Protection
Figure
5
59.). While the Chip Erase cycle is in
6
S25FL016K_00_02 September 8, 2010
7.25.
7
Mode 3
Mode 0

Related parts for S25FL016K0XMFI011