S25FL016K0XMFI041 Spansion Inc., S25FL016K0XMFI041 Datasheet - Page 12

• Manufacturer Part Number: S25FL016K0XMFI041
• Description: MEMORY, FLASH, 16M, 3V, SPI, 8SOIC
• Manufacturer: Spansion Inc.

Specifications of S25FL016K0XMFI041

• Memory Size: 16Mbit
• Clock Frequency: 104MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: SO
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Interface: SPI
• Memory Type: RoHS Compliant
• Memory Configuration: 8K X 256 Bytes
• Interface Type: SPI
• Rohs Compliant: Yes

5.
5.1
5.2
12
5.1.1
5.1.2
5.1.3
5.1.4
Functional Description
SPI Operations
Write Protection
Standard SPI Instructions
Dual SPI Instructions
Quad SPI Instructions
Hold Function
The S25FL016K is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK),
Chip Select (CS#), Serial Data Input (SI) and Serial Data Output (SO). Standard SPI instructions use the SI
input pin to serially write instructions, addresses or data to the device on the rising edge of CLK. The SO
output pin is used to read data or status from the device on the falling edge CLK.
SPI bus operation Mode 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode
3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data is not being
transferred to the Serial Flash. For Mode 0, the CLK signal is normally low on the falling and rising edges of
CS#. For Mode 3, the CLK signal is normally high on the falling and rising edges of CS#.
The S25FL016K supports Dual SPI operation when using the “Fast Read Dual Output (3Bh)” and “Fast Read
Dual I/O (BBh)” instructions. These instructions allow data to be transferred to or from the device at two to
three times the rate of ordinary Serial Flash devices. The Dual SPI Read instructions are ideal for quickly
downloading code to RAM upon power-up (code-shadowing) or for executing non-speed-critical code directly
from the SPI bus (XIP). When using Dual SPI instructions, the SI and SO pins become bidirectional I/O pins:
IO0 and IO1.
The S25FL016K supports Quad SPI operation when using the “Fast Read Quad Output (6Bh)”, “Fast Read
Quad I/O (EBh)”, “Word Read Quad I/O (E7h)” and “Octal Word Read Quad I/O (E3h)” instructions. These
instructions allow data to be transferred to or from the device four to six times the rate of ordinary Serial
Flash. The Quad Read instructions offer a significant improvement in continuous and random access transfer
rates allowing fast code-shadowing to RAM or execution directly from the SPI bus (XIP). When using Quad
SPI instructions the SI and SO pins become bidirectional IO0 and IO1, and the WP# and HOLD# pins
become IO2 and IO3 respectively. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in
Status Register-2 to be set.
For Standard SPI and Dual SPI operations, the HOLD# signal allows the S25FL016K operation to be paused
while it is actively selected (when CS# is low). The HOLD# function may be useful in cases where the SPI
data and clock signals are shared with other devices. For example, consider if the page buffer was only
partially written when a priority interrupt requires use of the SPI bus. In this case the HOLD# function can
save the state of the instruction and the data in the buffer so programming can resume where it left off once
the bus is available again. The HOLD# function is only available for standard SPI and Dual SPI operation, not
during Quad SPI.
To initiate a HOLD# condition, the device must be selected with CS# low. A HOLD# condition will activate on
the falling edge of the HOLD# signal if the CLK signal is already low. If the CLK is not already low the HOLD#
condition will activate after the next falling edge of CLK. The HOLD# condition will terminate on the rising
edge of the HOLD# signal if the CLK signal is already low. If the CLK is not already low the HOLD# condition
will terminate after the next falling edge of CLK. During a HOLD# condition, the Serial Data Output (SO) is
high impedance, and Serial Data Input (SI) and Serial Clock (CLK) are ignored. The Chip Select (CS#) signal
should be kept active (low) for the full duration of the HOLD# operation to avoid resetting the internal logic
state of the device.
Applications that use non-volatile memory must take into consideration the possibility of noise and other
adverse system conditions that may compromise data integrity. To address this concern, the S25FL016K
provides several means to protect the data from inadvertent writes.
D a t a
S25FL016K
S h e e t
( P r e l i m i n a r y )
S25FL016K_00_02 September 8, 2010