S25FL016K0XMFI041 Spansion Inc., S25FL016K0XMFI041 Datasheet - Page 21

• Manufacturer Part Number: S25FL016K0XMFI041
• Description: MEMORY, FLASH, 16M, 3V, SPI, 8SOIC
• Manufacturer: Spansion Inc.

Specifications of S25FL016K0XMFI041

• Memory Size: 16Mbit
• Clock Frequency: 104MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: SO
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Interface: SPI
• Memory Type: RoHS Compliant
• Memory Configuration: 8K X 256 Bytes
• Interface Type: SPI
• Rohs Compliant: Yes

7.2
7.3
September 8, 2010 S25FL016K_00_02
Write Enable for Volatile Status Register (50h)
Write Disable (04h)
The non-volatile Status Register bits described in
to as volatile bits. This gives more flexibility to change the system configuration and memory protection
schemes quickly without waiting for the typical non-volatile bit write cycles or affecting the endurance of the
Status Register non-volatile bits. To write the volatile values into the Status Register bits, the Write Enable for
Volatile Status Register (50h) instruction must be issued prior to a Write Status Register (01h) instruction.
Write Enable for Volatile Status Register instruction
it is only valid for the Write Status Register instruction to change the volatile Status Register bit values.
The Write Disable instruction (Figure 6) resets the Write Enable Latch (WEL) bit in the Status Register to a 0.
The Write Disable instruction is entered by driving CS# low, shifting the instruction code “04h” into the SI pin
and then driving CS# high. Note that the WEL bit is automatically reset after Power-up and upon completion
of the Write Status Register, Erase/Program Security Registers, Page Program, Quad Page Program, Sector
Erase, Block Erase and Chip Erase instructions.
CS#
CLK
CS#
CLK
SO
SO
SI
SI
D a t a
Figure 7.2 Write Enable for Volatile Status Register Instruction Sequence Diagram
Mode 3
Mode 0
Mode 3
Mode 0
S h e e t
Figure 7.3 Write Disable Instruction Sequence Diagram
( P r e l i m i n a r y )
0
0
S25FL016K
1
1
2
Instruction (50h)
High Impedance
Instruction (04h)
High Impedance
2
Section 6.1, Status Register on page 14
3
(Figure
3
4
4
5
7.2) will not set the Write Enable Latch (WEL) bit,
6
5
7
6
7
Mode 0
Mode 3
Mode 3
Mode 0
can also be written
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