S25FL016K0XMFI041 Spansion Inc., S25FL016K0XMFI041 Datasheet - Page 31

• Manufacturer Part Number: S25FL016K0XMFI041
• Description: MEMORY, FLASH, 16M, 3V, SPI, 8SOIC
• Manufacturer: Spansion Inc.

Specifications of S25FL016K0XMFI041

• Memory Size: 16Mbit
• Clock Frequency: 104MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: SO
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Interface: SPI
• Memory Type: RoHS Compliant
• Memory Configuration: 8K X 256 Bytes
• Interface Type: SPI
• Rohs Compliant: Yes

7.12
September 8, 2010 S25FL016K_00_02
Word Read Quad I/O (E7h)
The Word Read Quad I/O (E7h) instruction is similar to the Fast Read Quad I/O (EBh) instruction except that
the lowest Address bit (A0) must equal 0 and only two Dummy clock are required prior to the data output. The
Quad I/O dramatically reduces instruction overhead allowing faster random access for code execution (XIP)
directly from the Quad SPI. The Quad Enable bit (QE) of Status Register-2 must be set to enable the Word
Read Quad I/O Instruction.
Word Read Quad I/O with “Continuous Read Mode”
The Word Read Quad I/O instruction can further reduce instruction overhead through setting the “Continuous
Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in
(M7-4) controls the length of the next Fast Read Quad I/O instruction through the inclusion or exclusion of the
first byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However, the IO pins should
be high-impedance prior to the falling edge of the first data out clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after CS# is
raised and then lowered) does not require the E7h instruction code, as shown in
the instruction sequence by eight clocks and allows the Read address to be immediately entered after CS# is
asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction (after CS# is
raised and then lowered) requires the first byte instruction code, thus returning to normal operation. A
“Continuous Read Mode” Reset instruction can also be used to reset (M7-0) before issuing normal
instructions (see
CLK
IO3
CS#
IO1
IO2
IO0
Mode 3
Mode 0
Figure 7.14 Word Read Quad I/O Instruction Sequence (Initial instruction or previous M5-4 10)
D a t a
0
Section 7.16, Continuous Read Mode Reset (FFh or FFFFh) on page
1
Instruction (E7h)
2
S h e e t
3
4
5
( P r e l i m i n a r y )
6
S25FL016K
7
A23-16
4
6
5
7
8
3
0
2
1
9
4
6
5
7
10
A15-8
2
3
0
1
11 12 13 14
4
5
6
7
A7-0
2
0
1
3
4
5
6
7
M7-0
1
2
3
0
15
Dummy
16 17 18
Figure
6
7
4
5
7.14. The upper nibble of the
Byte 1
Figure
1
2
3
0
19 20 21 22
IO Switches from
Input to Output
5
6
Byte 2
4
7
36).
7.15. This reduces
2
1
3
0
Byte 3
4
6
5
7
0
2
1
3
23
4
5
6
7
3
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