SST25VF040B-50-4I-QAF SILICON STORAGE TECHNOLOGY, SST25VF040B-50-4I-QAF Datasheet
SST25VF040B-50-4I-QAF
Specifications of SST25VF040B-50-4I-QAF
Related parts for SST25VF040B-50-4I-QAF
SST25VF040B-50-4I-QAF Summary of contents
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... Erase or Program operation is less than alternative flash memory technologies. The SST25VF040B device is offered in both 8-lead SOIC (200 mils) and 8-contact WSON (6mm x 5mm) packages. See Figure 1 for pin assignments. The SST logo and SuperFlash are registered Trademarks of Silicon Storage Technology, Inc. ...
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... Data Sheet UNCTIONAL LOCK IAGRAM Address Buffers and Latches CE# ©2006 Silicon Storage Technology, Inc Decoder Control Logic Serial Interface SCK SI SO WP# HOLD Mbit SPI Serial Flash SST25VF040B SuperFlash Memory Y - Decoder I/O Buffers and Data Latches 1295 B1.0 S71295-01-000 1/06 ...
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... The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register. HOLD# Hold To temporarily stop serial communication with SPI flash memory without resetting the device. V Power Supply To provide power supply voltage: 2.7-3.6V for SST25VF040B DD V Ground SS ©2006 Silicon Storage Technology, Inc ...
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... Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). The SST25VF040B supports both Mode 0 (0,0) and Mode 3 (1,1) of SPI bus operations. The difference between the two modes, as shown in Figure 2, is the state of the SCK signal when the bus master is in Stand-by mode and no data is being transferred ...
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... W OLD ONDITION Write Protection SST25VF040B provides software Write protection. The Write Protect pin (WP#) enables or disables the lock-down function of the status register. The Block-Protection bits (BP3, BP2, BP1, BP0, and BPL) in the status register pro- vide Write protection to the memory array and the status register ...
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... Power- Auto Address Increment (AAI) The Auto Address Increment Programming-Status bit pro- vides status on whether the device is in AAI programming mode or Byte-Program mode. The default at power up is Byte-Program mode. 6 SST25VF040B Read/Write R R R/W R/W R/W R/W R R/W T3.0 1295 S71295-01-000 1/06 ...
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... Lock-Down (BPL) bit. When BPL is set prevents any further alteration of the BPL, BP3, BP2, BP1, and BP0 bits. When the WP# pin is driven high (V effect and its value is “Don’t Care”. After power-up, the BPL bit is reset SST25VF040B LOCK ROTECTION FOR 2 Status Register Bit BP3 BP2 ...
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... Data Sheet Instructions Instructions are used to read, write (Erase and Program), and configure the SST25VF040B. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to executing any Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, Write-Status-Register, or Chip-Erase instruc- tions, the Write-Enable (WREN) instruction must be exe- cuted first ...
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... Mbit SPI Serial Flash SST25VF040B Read (25 MHz) The Read instruction, 03H, supports MHz Read. The device outputs the data starting from the specified address location. The data output stream is continuous through all addresses until terminated by a low to high tran- sition on CE#. The internal address pointer will automati- cally increment until the highest memory address is reached ...
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... Once the data from address location 7FFFFH has been read, the next output will be from address location 00000H ADD. ADD. ADD. X MSB MSB EQUENCE 10 4 Mbit SPI Serial Flash SST25VF040B N+1 N+2 N+3 N OUT OUT OUT OUT OUT 1295 HSRdSeq.0 ...
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... Mbit SPI Serial Flash SST25VF040B Byte-Program The Byte-Program instruction programs the bits in the selected byte to the desired data. The selected byte must be in the erased state (FFH) when initiating a Program operation. A Byte-Program instruction applied to a pro- tected memory area will be ignored. ...
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... SO pin to output Software Status Register data during AAI Word programming. (see Figure Following the 0 CE with 23 1 SCK =1. CE# must be 0 FIGURE 7: E CE# SCK FIGURE Mbit SPI Serial Flash SST25VF040B MODE MODE MSB HIGH IMPEDANCE SO 1295 EnableSO RY/BY# NABLE AS ARDWARE AAI P DURING ROGRAMMING ...
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... Mbit SPI Serial Flash SST25VF040B CE MODE 3 SCK MODE Load AAI command, Address, 2 bytes data 2 SO Note: 1. Valid commands during AAI programming: AAI command or WRDI command 2. User must configure the SO pin to output Flash Busy status during AAI programming FIGURE UTO DDRESS NCREMENT ...
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... The user may poll the Busy bit in the software status regis- ter or wait T Sector-Erase cycle. See Figure 11 for the Sector-Erase sequence Most ADD. ADD. MSB MSB HIGH IMPEDANCE 14 4 Mbit SPI Serial Flash SST25VF040B ), remaining address bits can for the completion of the internal self-timed ADD. 1295 SecErase.0 S71295-01-000 IH. 1/06 ...
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... Mbit SPI Serial Flash SST25VF040B 32-KByte and 64-KByte Block-Erase The 32-KByte Block-Erase instruction clears all bits in the selected 32 KByte block to FFH. A Block-Erase instruction applied to a protected memory area will be ignored. The 64-KByte Block-Erase instruction clears all bits in the selected 64 KByte block to FFH. A Block-Erase instruction applied to a protected memory area will be ignored ...
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... Status-Register is continuous with ongoing clock cycles until it is terminated by a low to high transition of the CE#. See Figure 15 for the RDSR instruction sequence Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MSB (RDSR) S EQUENCE 16 4 Mbit SPI Serial Flash SST25VF040B Status 1295 RDSRseq.0 Register Out S71295-01-000 CE 1/06 ...
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... Mbit SPI Serial Flash SST25VF040B Write-Enable (WREN) The Write-Enable (WREN) instruction sets the Write- Enable-Latch bit in the Status Register to 1 allowing Write operations to occur. The WREN instruction must be exe- cuted prior to any Write (Program/Erase) operation. The WREN instruction may also be used to allow execution of ...
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... BP2 bits at the same time. See Table 2 for a summary description of WP# and BPL functions MODE 3 MODE 0 01 MSB HIGH IMPEDANCE -R (EWSR) EGISTER (WRSR) S AND RITE TATUS EGISTER 18 4 Mbit SPI Serial Flash SST25VF040B ) prior to the IH STATUS REGISTER MSB 1295 EWSR.0 EQUENCE S71295-01-000 1/06 ...
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... SST25VF040B JEDEC Read-ID The JEDEC Read-ID instruction identifies the device as SST25VF040B and the manufacturer as SST. The device information can be read from executing the 8-bit command, 9FH. Following the JEDEC Read-ID instruction, the 8-bit manufacturer’s ID, BFH, is output from the device. After that, a 16-bit device ID is shifted out on the SO pin ...
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... Data Sheet Read-ID (RDID) The Read-ID instruction (RDID) identifies the devices as SST25VF040B and manufacturer as SST. This command is backward compatible to all SST25xFxxxA devices and should be used as default device identification when multi- ple versions of SPI Serial Flash devices are used in a design. The device information can be read from executing ...
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... Mbit SPI Serial Flash SST25VF040B ELECTRICAL SPECIFICATIONS Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55° ...
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... Max 0.1 0 100 and T requirements SCKH SCKL 22 4 Mbit SPI Serial Flash SST25VF040B Test Condition Maximum OUT T10.0 1295 Units Test Method Cycles JEDEC Standard A117 Years JEDEC Standard A103 mA JEDEC Standard 78 T11.0 1295 50 MHz Min Max Units 50 MHz 0.1 V/ns ...
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... Mbit SPI Serial Flash SST25VF040B CE# T CHH T CES SCK MSB SI SO HIGH-Z FIGURE 21 ERIAL NPUT IMING CE# T SCKH SCK T CLZ SO SI FIGURE 22 ERIAL UTPUT IMING ©2006 Silicon Storage Technology, Inc. T SCKF T SCKR D IAGRAM T SCKL T OH MSB IAGRAM 23 Data Sheet T CPH T T CEH ...
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... Commands may not be accepted or properly interpreted by the device. V Min DD FIGURE 24 OWER UP IMING ©2006 Silicon Storage Technology, Inc HHH HLS T HLH PU-READ Device fully accessible T PU-WRITE D IAGRAM 24 4 Mbit SPI Serial Flash SST25VF040B T HHS T LZ 1295 Hold.0 Time 1295 PwrUp.0 S71295-01-000 1/06 ...
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... Mbit SPI Serial Flash SST25VF040B V IHT INPUT V ILT AC test inputs are driven at V (0.9V IHT for inputs and outputs are V (0.6V HT FIGURE 25 NPUT UTPUT FIGURE 26 EST OAD XAMPLE ©2006 Silicon Storage Technology, Inc REFERENCE POINTS for a logic “1” and V (0.1V ...
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... XXX X - Valid combinations for SST25VF040B SST25VF040B-50-4C-S2AF SST25VF040B-50-4C-QAF SST25VF040B-50-4I-S2AF SST25VF040B-50-4I-QAF Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ©2006 Silicon Storage Technology, Inc S2A F ...
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... Mbit SPI Serial Flash SST25VF040B PACKAGING DIAGRAMS Pin #1 TOP VIEW Identifier 5.40 5.15 5.40 5.15 8.10 7.70 Note: 1. All linear dimensions are in millimeters (max/min). 2. Coplanarity: 0 Maximum allowable mold flash is 0. the package ends and 0.25 mm between leads LEAD MALL UTLINE NTEGRATED ...
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... SS of the unit (WSON) UTLINE O LEAD Description www.SuperFlash.com or www.sst.com 28 4 Mbit SPI Serial Flash SST25VF040B BOTTOM VIEW Pin #1 1.27 BSC 4.0 0.48 0.35 3.4 0.70 0.50 CROSS SECTION 0.80 0.70 8-wson-5x6-QA-9.0 Date Sep 2005 Jan 2006 S71295-01-000 ...