SST25VF040B-80-4I-SAE SILICON STORAGE TECHNOLOGY, SST25VF040B-80-4I-SAE Datasheet
SST25VF040B-80-4I-SAE
Specifications of SST25VF040B-80-4I-SAE
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SST25VF040B-80-4I-SAE Summary of contents
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... SST's 25 series Serial Flash family features a four-wire, SPI-compatible inter- face that allows for a low pin-count package which occupies less board space and ultimately lowers total system costs. The SST25VF040B devices are enhanced with improved operating frequency which lowers power consump- tion. SST25VF040B SPI serial flash memories are manufactured with SST's proprietary, high-performance CMOS SuperFlash technology ...
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... Erase or Program operation is less than alternative flash memory technologies. The SST25VF040B device is offered in an 8-lead SOIC (200 mils), 8-lead SOIC (150 mils), and 8-con- tact WSON (6mm x 5mm) packages. See Figure 2 for pin assignments. ...
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... Block Diagram Figure 1: Functional Block Diagram ©2011 Silicon Storage Technology, Inc Decoder Address Buffers and Latches Control Logic Serial Interface CE# SCK Mbit SPI Serial Flash SST25VF040B Data Sheet SuperFlash Memory Y - Decoder I/O Buffers and Data Latches WP# HOLD# 1295 B1.0 S71295-06-000 02/11 ...
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... The Write Protect (WP#) pin is used to enable/disable BPL bit in the status reg- ister. To temporarily stop serial communication with SPI flash memory without reset- ting the device. To provide power supply voltage: 2.7-3.6V for SST25VF040B 4 4 Mbit SPI Serial Flash SST25VF040B Data Sheet ...
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... Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). The SST25VF040B supports both Mode 0 (0,0) and Mode 3 (1,1) of SPI bus operations. The difference between the two modes, as shown in Figure 3, is the state of the SCK signal when the bus master is in Stand-by mode and no data is being transferred ...
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... Figure 4: Hold Condition Waveform Write Protection SST25VF040B provides software Write protection. The Write Protect pin (WP#) enables or disables the lock-down function of the status register. The Block-Protection bits (BP3, BP2, BP1, BP0, and BPL) in the status register provide Write protection to the memory array and the status register. See Table 4 for the Block-Protection description ...
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... Indicate current level of block write protection (See Table 4) Indicate current level of block write protection (See Table 4) Auto Address Increment Programming status 1 = AAI programming mode 0 = Byte-Program mode 1 = BP3, BP2, BP1, BP0 are read-only bits 0 = BP3, BP2, BP1, BP0 are read/writable 7 SST25VF040B Data Sheet Default at Power-up Read/Write ...
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... Silicon Storage Technology, Inc. ), enables the Block-Protection-Lock-Down (BPL) bit. When BPL is set Status Register Bit BP3 BP2 BP1 Mbit SPI Serial Flash SST25VF040B Data Sheet 1 SST25VF040B FOR 2 Protected Memory Address BP0 4 Mbit 0 None 1 70000H-7FFFFH 0 60000H-7FFFFH 1 40000H-7FFFFH 0 00000H-7FFFFH 1 00000H-7FFFFH 0 00000H-7FFFFH 1 00000H-7FFFFH S71295-06-000 T4.0 1295 02/11 ...
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... A Microchip Technology Company Instructions Instructions are used to read, write (Erase and Program), and configure the SST25VF040B. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to execut- ing any Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, Write- Status-Register, or Chip-Erase instructions, the Write-Enable (WREN) instruction must be executed first ...
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... ID and device ID output stream is continuous until terminated by a low-to-high transition on CE#. Read (25/33 MHz) The Read instruction, 03H, supports MHz (for SST25VF040B-50-xx-xxF MHz (for SST25VF040B-80-xx-xxE) Read. The device outputs the data starting from the specified address location. The data output stream is continuous through all addresses until terminated by a low to high transition on CE# ...
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... A Microchip Technology Company High-Speed-Read (50/80 MHz) The High-Speed-Read instruction supporting MHz (for SST25VF040B-50-xx-xxF MHz (for SST25VF040B-80-xx-xxE) Read is initiated by executing an 8-bit command, 0BH, followed by address bits [A Speed-Read cycle. See Figure 6 for the High-Speed-Read sequence. Following a dummy cycle, the High-Speed-Read instruction outputs the data starting from the speci- fied address location ...
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... Enable-Latch bit (WEL=0) and AAI bit. Then execute the 8-bit DBSY command, 80H, to disable RY/ BY# status during the AAI command. See Figures 9 and 10. ©2011 Silicon Storage Technology, Inc. 4 Mbit SPI Serial Flash -A ] with The Hardware End-of-Write detection method is described in the BP. 12 SST25VF040B Data Sheet BP Fol with A =0, the second 23 ...
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... Figure 8: Enable SO as Hardware RY/BY# During AAI Programming Figure 9: Disable SO as Hardware RY/BY# During AAI Programming ©2011 Silicon Storage Technology, Inc. 4 Mbit SPI Serial Flash CE# MODE SCK MODE MSB HIGH IMPEDANCE SO 1271 EnableSO.0 CE# MODE MODE 0 SCK 80 SI MSB HIGH IMPEDANCE SO 1271 DisableSO.0 13 SST25VF040B Data Sheet S71295-06-000 02/11 ...
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... SCK cont cont. AD n-1 Last 2 Data Bytes SO cont. Check for Flash Busy Status to load next valid Wait T register to load next valid Mbit SPI Serial Flash SST25VF040B Check for Flash Busy Status to load next valid command WRDI RDSR DBSY WRDI followed by DBSY ...
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... Silicon Storage Technology, Inc. 4 Mbit SPI Serial Flash -A ]. Address bits [ remaining address bits can CE# MODE SCK MODE 0 20 ADD. SI MSB MSB HIGH IMPEDANCE SO 15 SST25VF040B Data Sheet = Most Significant address) are used CE# must be driven high IL IH ADD. ADD. 1295 SecErase.0 S71295-06-000 02/11 ...
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... CE# must be driven high before the instruction is executed. The 64-KByte Block- IL IH. ), remaining address bits can CE# MODE MODE 0 SCK 52 SI MSB HIGH IMPEDANCE SO CE# MODE MODE 0 SCK D8 SI MSB HIGH IMPEDANCE Mbit SPI Serial Flash SST25VF040B Data Sheet - remaining Address bits CE# must ADDR ADDR ADDR MSB 1295 32KBklEr ADDR ...
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... Figure 16:Read-Status-Register (RDSR) Sequence ©2011 Silicon Storage Technology, Inc. CE# MODE SCK MODE MSB HIGH IMPEDANCE MSB HIGH IMPEDANCE 17 4 Mbit SPI Serial Flash SST25VF040B Data Sheet 1295 ChEr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MSB Status 1295 RDSRseq.0 Register Out S71295-06-000 02/11 ...
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... Figure 18:Write Disable (WRDI) Sequence ©2011 Silicon Storage Technology, Inc. 4 Mbit SPI Serial Flash CE# MODE MODE 0 SCK 06 SI MSB HIGH IMPEDANCE SO 1295 WREN.0 CE# MODE MODE 0 SCK 04 SI MSB HIGH IMPEDANCE SO 1295 WRDI.0 18 SST25VF040B Data Sheet after executing the WRDI BP S71295-06-000 02/11 ...
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... Figure 19:Enable-Write-Status-Register (EWSR) or Write-Enable (WREN) and Write-Sta- tus-Register (WRSR) Sequence ©2011 Silicon Storage Technology, Inc. ) prior to the low-to-high transition of the CE# pin at the end MODE 3 MODE MSB MSB HIGH IMPEDANCE 19 4 Mbit SPI Serial Flash SST25VF040B Data Sheet STATUS REGISTER MSB 1295 EWSR.0 S71295-06-000 02/11 ...
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... Read-ID instruction, the 8-bit manufacturer’s ID, BFH, is output from the device. After that, a 16-bit device ID is shifted out on the SO pin. Byte 1, BFH, identifies the manufacturer as SST. Byte 2, 25H, identifies the memory type as SPI Serial Flash. Byte 3, 8DH, identifies the device as SST25VF040B. The instruction sequence is shown in Figure 20. The JEDEC Read ID instruction is terminated by a low to high transition on CE# at any time during data output ...
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... A Microchip Technology Company Read-ID (RDID) The Read-ID instruction (RDID) identifies the devices as SST25VF040B and manufacturer as SST. This command is backward compatible to all SST25xFxxxA devices and should be used as default device identification when multiple versions of SPI Serial Flash devices are used in a design. The ...
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... Input Rise/Fall Time 5ns Limits Min Max Units 0.8 0 0.2 0 Mbit SPI Serial Flash SST25VF040B Data Sheet V DD 2.7-3.6V 2.7-3.6V Output Load Test Conditions mA CE#=0.1 V /0.9 V @25 MHz, SO=open CE#=0.1 V /0.9 V @50 MHz, SO=open DD DD ...
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... V Min to Write Operation 25°C, f=1 Mhz, other pins open) A Description Output Pin Capacitance Input Capacitance Parameter Minimum Specification Endurance Data Retention Latch Mbit SPI Serial Flash SST25VF040B Test Conditions mA CE#=0.1 V /0.9 V @33 MHz, SO=open CE#=0.1 V /0.9 V @80 MHz, SO=open CE#=V DD µ ...
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... Maximum clock frequency for Read Instruction, 03H MHz 2. Maximum Rise and Fall time may be limited Relative to SCK. ©2011 Silicon Storage Technology, Inc. 4 Mbit SPI Serial Flash 25 MHz Parameter Min 18 18 0.1 0 and T requirements SCKH SCKL 24 SST25VF040B Data Sheet 50 MHz Max Min Max 0.1 0 ...
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... Maximum clock frequency for Read Instruction, 03H MHz 2. Maximum Rise and Fall time may be limited Relative to SCK. ©2011 Silicon Storage Technology, Inc. 4 Mbit SPI Serial Flash 33 MHz Parameter Min 13 13 0.1 0 and T requirements SCKH SCKL 25 SST25VF040B Data Sheet 80 MHz Max Min Max Units 33 80 MHz 0.1 V/ns 0.1 V/ ...
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... Silicon Storage Technology, Inc. T CES SCKR MSB HIGH SCKH SCKL CLZ MSB HHH HLS Mbit SPI Serial Flash SST25VF040B Data Sheet T CPH T T CEH CHS T SCKF LSB HIGH-Z T CHZ LSB 1295 SerOut.0 T HHS T HLH T LZ S71295-06-000 1295 SerIn.0 1295 Hold.0 02/11 ...
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... Min to Write Operation DD Chip selection is not allowed. Commands may not be accepted or properly interpreted by the device. T PU-READ T PU-WRITE 27 4 Mbit SPI Serial Flash SST25VF040B Data Sheet ramp rate of greater than 1V per 100 DD Minimum 100 100 Device fully accessible Time 1295 PwrUp.0 S71295-06-000 Units µ ...
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... INPUT REFERENCE POINTS V LT (0.9V ) for a logic “1” and V IHT DD HT 90%) are <5 ns. TO DUT 28 4 Mbit SPI Serial Flash SST25VF040B V HT OUTPUT V LT 1295 IORef.0 (0.1V ) for a logic “0”. Measure- ILT DD (0.6V ) and V (0.4V ). Input rise and fall ...
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... Product Series 25 = Serial Peripheral Interface flash memory 1. Environmental suffix “F” denotes non-Pb/non-SN solder. SST non-Pb/non-Sn solder devices are “RoHS Compliant”. 2. Environmental suffix “E” denotes non-Pb solder. SST non-Pb solder devices are “RoHS Compliant”. SST25VF040B-50-4C-SAF SST25VF040B-50-4I-SAF SST25VF040B-80-4I-SAE S71295-06-000 02/11 ...
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... SST Package Code: S2A ©2011 Silicon Storage Technology, Inc. TOP VIEW SIDE VIEW 5.40 5.15 2.16 8.10 1.75 7.70 0.25 0. Mbit SPI Serial Flash SST25VF040B Data Sheet 0.50 0.35 1.27 BSC 0.25 END VIEW 0.05 08-soic-EIAJ-S2A-3 1mm S71295-06-000 0° 8° 0.80 ...
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... SST Package Code: SA ©2011 Silicon Storage Technology, Inc. SIDE VIEW TOP VIEW 1.27 BSC 0.25 0.10 4.00 3.80 1.75 6.20 1.35 5. Mbit SPI Serial Flash SST25VF040B Data Sheet 7° 4 places 0.51 0.33 END VIEW 45° 4 places 0.25 0.19 1.27 0.40 08-soic-5x6-SA-8 1mm S71295-06-000 7° ...
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... Silicon Storage Technology, Inc. TOP VIEW SIDE VIEW 5.00 0 .10 6.00 0.10 0.80 0.70 leads the unit Mbit SPI Serial Flash SST25VF040B BOTTOM VIEW 0.2 4.0 0.076 3.4 0.05 Max CROSS SECTION 1mm 8-wson-5x6-QA-9.0 S71295-06-000 Data Sheet Pin #1 1.27 BSC ...
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... Modified High-Speed-Read values in Table 5 on page 9 and “High- Speed-Read (50/80 MHz)” on page 11 05 • Added 50/33 MHz information throughout. • Separated AC and DC Characteristics for SST25VF040B-50-4C-xxxF & SST25VF040B-80-4I-xxxE 06 • Updated “Auto Address Increment (AAI) Word-Program”, “End-of-Write Detection”, and “Hardware End-of-Write Detection” on page 12. ...