PIC16LF1827-I/MV Microchip Technology, PIC16LF1827-I/MV Datasheet
PIC16LF1827-I/MV
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PIC16LF1827-I/MV Summary of contents
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... Flash Microcontrollers 2010 Microchip Technology Inc. PIC16F/LF1826/27 with nanoWatt XLP Technology Preliminary Data Sheet DS41391C ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... In-Circuit Serial Programming™ (ICSP™) via two pins • In-Circuit Debug (ICD) via two pins • Enhance Low-Voltage Programming • Power-Saving Sleep mode 2010 Microchip Technology Inc. PIC16F/LF1826/27 Extreme Low-Power Management PIC16LF1826/27 with nanoWatt XLP: • Sleep mode • ...
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... PIC16F/LF1826/27 PIC16F/LF1826/27 Family Types Program Data Memory Memory PIC16LF1826 2K 256 PIC16F1826 2K 256 PIC16LF1827 4K 384 PIC16F1827 4K 384 Note 1: One pin is input only. DS41391C-page 4 256 2/1 256 2/1 256 4/1 256 4/1 Preliminary — — Yes — — Yes Yes Yes 2010 Microchip Technology Inc. ...
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Pin Diagram – 18-Pin PDIP, SOIC PIC16F/LF1826/27) ( PDIP, SOIC RA2/AN2/CPS2/C12IN2-/C12IN+/V RA3/AN3/CPS3/C12IN3-/C1IN+/V RA4/AN4/CPS4/C2OUT/T0CKI/CCP4 RB0/SRI/T1G/CCP1 RB1/AN11/CPS11/RX (1) (1) (1) RB2/AN10/CPS10/MDMIN/TX /CK /RX RB3/AN9/CPS9/MDOUT/CCP1 Note 1: Pin feature is dependent on device configuration. 2: ECCP2, CCP3, CCP4, MSSP2 functions are only available ...
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... Pin feature is dependent on device configuration. 2: ECCP2, CCP3, CCP4, MSSP2 functions are only available on the PIC16F/LF1827. DS41391C-page 6 PIC16F/LF1826/27 RA7/OSC1/CLKIN/P1C 2 20 RA6/OSC2/CLKOUT/CLKR/P1D PIC16F/LF1826/ RB7/AN6/CPS6/T1OSO/P1D 7 15 RB6/AN5/CPS5/T1CKI/T1OSI/P1C Preliminary (1) (1,2) (1,2) /CCP2 /P2A (1) (1,2) (1) /P2B /SDO1 (1) (1,2) /P2B /MDCIN1/ICSPDAT (1) (1,2) (1,2) /CCP2 /P2A /ICSPCLK 2010 Microchip Technology Inc. ...
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TABLE 1: 18/20/28-PIN SUMMARY (PIC16F/LF1826/27) RA0 AN0 — RA1 AN1 — RA2 AN2 V - REF DACOUT RA3 AN3 V + REF RA4 3 ...
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... Packaging Information.............................................................................................................................................................. 383 Appendix A: Revision History............................................................................................................................................................. 393 Appendix B: Device Differences......................................................................................................................................................... 393 Index .................................................................................................................................................................................................. 395 The Microchip Web Site ..................................................................................................................................................................... 403 Customer Change Notification Service .............................................................................................................................................. 403 Customer Support .............................................................................................................................................................................. 403 Reader Response .............................................................................................................................................................................. 404 Product Identification System............................................................................................................................................................. 405 DS41391C-page 8 ) ................................................................................................................................ 325 ™ Preliminary 2010 Microchip Technology Inc. ...
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... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. 2010 Microchip Technology Inc. PIC16F/LF1826/27 Preliminary DS41391C-page 9 ...
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... PIC16F/LF1826/27 NOTES: DS41391C-page 10 Preliminary 2010 Microchip Technology Inc. ...
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... Capture/Compare/PWM Modules ECCP1 ECCP2 CCP3 CCP4 Comparators C1 C2 Master Synchronous Serial Ports MSSP1 MSSP2 Timers Timer0 Timer1 Timer2 Timer4 Timer6 2010 Microchip Technology Inc. PIC16F/LF1826/27 of the ● ● ● ● ● ● ● ● ● ● ● ● ● ● ...
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... See applicable chapters for more information on peripherals. 2: See Table 1-1 for peripherals available on specific devices. DS41391C-page 12 Program Flash Memory RAM CPU (Figure 2-1) Timer2- Timer1 DAC Comparators Types Modulator FVR EUSART CapSense Preliminary EEPROM PORTA PORTB 2010 Microchip Technology Inc. ...
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... TTL = TTL compatible input High Voltage XTAL = Crystal Note 1: Pin functions can be moved using the APFCON0 or APFCON1 register. 2: Functions are only available on the PIC16F/LF1827. 3: Default function location. 2010 Microchip Technology Inc. PIC16F/LF1826/27 Input Output Type Type TTL CMOS General purpose I/O. ...
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... CMOS USART synchronous data C™ C™ data input/output 2. ST — SPI data input 2. — CMOS SPI data output 1. = Schmitt Trigger input with CMOS levels I Preliminary Description OD = Open Drain 2 2 C™ = Schmitt Trigger input with I C levels 2010 Microchip Technology Inc. ...
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... TTL = TTL compatible input High Voltage XTAL = Crystal Note 1: Pin functions can be moved using the APFCON0 or APFCON1 register. 2: Functions are only available on the PIC16F/LF1827. 3: Default function location. 2010 Microchip Technology Inc. PIC16F/LF1826/27 Input Output Type Type TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. ...
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... Functions are only available on the PIC16F/LF1827. 3: Default function location. DS41391C-page 16 Input Output Type Type Power — Positive supply. Power — Ground reference. = Schmitt Trigger input with CMOS levels I Preliminary Description OD = Open Drain 2 2 C™ = Schmitt Trigger input with I C levels 2010 Microchip Technology Inc. ...
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... FSRs. See Section 3.4 “Stack”for more details. 2.4 Instruction Set There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section 28.0 “Instruction Set Summary” for more details. 2010 Microchip Technology Inc. PIC16F/LF1826/27 Preliminary DS41391C-page 17 ...
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... Power-up Timer Oscillator Start-up Timer ALU ALU ALU Power- Reset Watchdog W reg Timer Brown-out Reset Preliminary RAM Addr 12 Indirect Addr 12 FSR0 Reg FSR reg FSR reg STATUS Reg STATUS reg STATUS reg MUX MUX MUX 2010 Microchip Technology Inc. ...
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... Section 11.0 “Data EEPROM and Flash Program Memory Control”. TABLE 3-1: DEVICE SIZES AND ADDRESSES Device PIC16F/LF1826 PIC16F/LF1827 2010 Microchip Technology Inc. PIC16F/LF1826/27 The following features are associated with access and control of program memory and data memory: memory in • PCL and PCLATH • ...
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... Memory 7FFFh Preliminary PROGRAM MEMORY MAP AND STACK FOR PIC16F/LF1827 PC<14:0> 15 Stack Level 0 Stack Level 1 Stack Level 15 Reset Vector 0000h Interrupt Vector 0004h 0005h Page 0 07FFh 0800h Page 1 0FFFh 1000h Rollover to Page 0 Rollover to Page 1 7FFFh 2010 Microchip Technology Inc. ...
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... The BRW instruction makes this type of table very sim- ple to implement. If your code must remain portable with previous generations of microcontrollers, then the BRW instruction is not available so the older table read method must be used. 2010 Microchip Technology Inc. PIC16F/LF1826/27 Preliminary DS41391C-page 21 ...
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... STATUS • FSR0 Low • FSR0 High • FSR1 Low • FSR1 High • BSR • WREG • PCLATH • INTCON Note: The core registers are the first 12 addresses of every data memory bank. “Indirect Preliminary 2010 Microchip Technology Inc. ...
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... For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register. 2010 Microchip Technology Inc. PIC16F/LF1826/27 For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as ‘ ...
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... DS41391C-page 24 3.2.5 DEVICE MEMORY MAPS The memory maps for the device family are as shown in Table 3-2. TABLE 3-2: MEMORY MAP TABLES Device PIC16F/LF1826/27 Preliminary 2010 Microchip Technology Inc. Banks Table No. 0-7 Table 3-3 8-15 Table 3-4 16-23 Table 3-5 24-31 ...
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TABLE 3-3: PIC16F/LF1826/27 MEMORY MAP, BANKS 0-7 BANK0 BANK1 000h INDF0 080h INDF0 100h 001h INDF1 081h INDF1 101h 002h PCL 082h PCL 102h 003h STATUS 083h STATUS 103h 004h FSR0L 084h FSR0L 104h 005h FSR0H 085h FSR0H 105h 006h ...
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TABLE 3-4: PIC16F/LF1826/27 MEMORY MAP, BANKS 8-15 BANK 8 BANK 9 INDF0 INDF0 400h 480h 500h INDF1 INDF1 401h 481h 501h PCL PCL 402h 482h 502h STATUS STATUS 403h 483h 503h FSR0L FSR0L 404h 484h 504h FSR0H FSR0H 405h 485h ...
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TABLE 3-5: PIC16F/LF1826/27 MEMORY MAP, BANKS 16-23) BANK16 BANK17 800h INDF0 880h INDF0 900h 801h INDF1 881h INDF1 901h 802h PCL 882h PCL 902h 803h STATUS 883h STATUS 903h 804h FSR0L 884h FSR0L 904h 805h FSR0H 885h FSR0H 905h 806h ...
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TABLE 3-6: PIC16F/LF1826/27 MEMORY MAP, BANKS 24-31 BANK 24 BANK 25 C00h INDF0 C80h INDF0 D00h C01h INDF1 C81h INDF1 D01h C02h PCL C82h PCL D02h C03h STATUS C83h STATUS D03h C04h FSR0L C84h FSR0L D04h C05h FSR0H C85h FSR0H ...
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... FECh FEDh STKPTR FEEh TOSL FEFh TOSH Legend: = Unimplemented data memory locations, read as ‘0’. 2010 Microchip Technology Inc. PIC16F/LF1826/27 3.2.6 SPECIAL FUNCTION REGISTERS SUMMARY The Special Function Register Summary for the device family are as follows: Device PIC16F/LF1826/27 Preliminary Bank(s) Page No ...
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... TMR1ON 0000 00-0 uuuu uu-u T1GSS1 T1GSS0 0000 0x00 uuuu uxuu 0000 0000 0000 0000 1111 1111 1111 1111 T2CKPS1 T2CKPS0 -000 0000 -000 0000 — — T0XCS 0--- 0000 0--- 0000 CPSCH1 CPSCH0 ---- 0000 ---- 0000 2010 Microchip Technology Inc. ...
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... ADCS2 09Fh — Unimplemented Legend unknown unchanged value depends on condition unimplemented reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: PIC16F/LF1827 only. 2: These registers can be addressed from any bank. 2010 Microchip Technology Inc. PIC16F/LF1826/27 Bit 5 Bit 4 Bit 3 Bit 2 — — ...
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... DACNSS 000- 00-0 000- 00-0 DACR1 DACR0 ---0 0000 ---0 0000 SRPS SRPR 0000 0000 0000 0000 SRRC2E SRRC1E 0000 0000 0000 0000 — — P1CSEL CCP1SEL 0000 0000 0000 0000 — TXCKSEL ---- ---0 ---- ---0 — — 2010 Microchip Technology Inc. ...
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... BAUDCON ABDOVF RCIDL Legend unknown unchanged value depends on condition unimplemented reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: PIC16F/LF1827 only. 2: These registers can be addressed from any bank. 2010 Microchip Technology Inc. PIC16F/LF1826/27 Bit 5 Bit 4 Bit 3 Bit 2 — — ...
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... ADD1 ADD0 0000 0000 0000 0000 MSK1 MSK0 1111 1111 1111 1111 UA BF 0000 0000 0000 0000 SSPM1 SSPM0 0000 0000 0000 0000 RSEN SEN 0000 0000 0000 0000 AHEN DHEN 0000 0000 0000 0000 2010 Microchip Technology Inc. ...
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... C4TSEL0 29Fh — Unimplemented Legend unknown unchanged value depends on condition unimplemented reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: PIC16F/LF1827 only. 2: These registers can be addressed from any bank. 2010 Microchip Technology Inc. PIC16F/LF1826/27 Bit 5 Bit 4 Bit 3 Bit 2 — — ...
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... CCP3M1 CCP3M0 --00 0000 --00 0000 — — — — — — — — xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP4M1 CCP4M0 --00 0000 --00 0000 — — — — — — — — — — 2010 Microchip Technology Inc. ...
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... MDCARH MDCHODIS MDCHPOL MDCHSYNC Legend unknown unchanged value depends on condition unimplemented reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: PIC16F/LF1827 only. 2: These registers can be addressed from any bank. 2010 Microchip Technology Inc. PIC16F/LF1826/27 Bit 5 Bit 4 Bit 3 Bit 2 — — ...
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... T4CKPS1 T4CKPS0 -000 0000 -000 0000 — — — — — — — — 0000 0000 0000 0000 1111 1111 1111 1111 T6CKPS1 T6CKPS0 -000 0000 -000 0000 — — 2010 Microchip Technology Inc. ...
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... Legend unknown unchanged value depends on condition unimplemented reserved. Shaded locations are unimplemented, read as ‘0’. Note 1: PIC16F/LF1827 only. 2: These registers can be addressed from any bank. 2010 Microchip Technology Inc. PIC16F/LF1826/27 Bit 5 Bit 4 Bit 3 Bit 2 — — ...
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... Microchip Technology Inc. ...
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... GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to the Application Note AN556, “Implementing a Table Read” (DS00556). 2010 Microchip Technology Inc. PIC16F/LF1826/27 3.3.3 COMPUTED FUNCTION CALLS A computed function CALL allows programs to maintain tables of functions and provide another way to execute state machines or look-up tables ...
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... TOSH/TOSL registers will return ‘ ’. If the Stack Overflow/Underflow Reset is 0x05 disabled, the TOSH/TOSL registers will 0x04 return the contents of stack address 0x0F. 0x03 0x02 0x01 0x00 STKPTR = 0x1F 0x1F 0x0000 Preliminary Stack Reset Disabled (STVREN = ) Stack Reset Enabled (STVREN = ) 2010 Microchip Technology Inc. ...
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... FIGURE 3-6: ACCESSING THE STACK EXAMPLE 2 TOSH:TOSL FIGURE 3-7: ACCESSING THE STACK EXAMPLE 3 TOSH:TOSL 2010 Microchip Technology Inc. PIC16F/LF1826/27 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A This figure shows the stack configuration 0x09 after the first If a 0x08 return address will be placed in the ...
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... Overflow/Underflow Reset is enabled, a Reset will occur and location 0x00 will Return Address 0x06 not be overwritten. Return Address 0x05 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address STKPTR = 0x10 Return Address 0x00 Preliminary or 2010 Microchip Technology Inc. ...
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... FIGURE 3-9: INDIRECT ADDRESSING FSR Address Range Note: Not all memory regions are completely implemented. Consult device memory tables for memory limits. 2010 Microchip Technology Inc. PIC16F/LF1826/27 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x0FFF 0x1000 Reserved 0x1FFF 0x2000 Linear Data Memory ...
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... FIGURE 3-10: TRADITIONAL DATA MEMORY MAP Direct Addressing From Opcode 4 BSR 6 0 Location Select Bank Select 0x00 0x7F DS41391C-page FSRxH Bank Select 0000 0001 0010 1111 Bank 0 Bank 1 Bank 2 Bank 31 Preliminary Indirect Addressing 0 7 FSRxL 0 Location Select 2010 Microchip Technology Inc. ...
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... FSRnL Location Select 0x2000 0x29AF 2010 Microchip Technology Inc. PIC16F/LF1826/27 3.5.3 PROGRAM FLASH MEMORY To make constant data access easier, the entire program Flash memory is mapped to the upper half of the FSR address space. When the MSB of FSRnH is set, the lower 15 bits are the address in program memory which will be accessed through INDF ...
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... PIC16F/LF1826/27 NOTES: DS41391C-page 48 Preliminary 2010 Microchip Technology Inc. ...
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... These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h. Note: The DEBUG bit in Configuration Word is managed automatically development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a '1'. 2010 Microchip Technology Inc. PIC16F/LF1826/27 by device Preliminary DS41391C-page 49 ...
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... R/P-1/1 R/P-1/1 R/P-1/1 WDTE1 WDTE0 FOSC2 U = Unimplemented bit, read as ‘1’ -n/n = Value at POR and BOR/Value at all other Resets P = Programmable bit (1) (2) (3) Pin Function Select bit (1) Preliminary R/P-1/1 R/P-1/1 CPD CP bit 7 R/P-1/1 R/P-1/1 FOSC1 FOSC0 bit 0 2010 Microchip Technology Inc. ...
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... Enabling Brown-out Reset does not automatically enable Power-up Timer. 2: The entire data EEPROM will be erased when the code protection is turned off during an erase. 3: The entire program memory will be erased when the code protection is turned off. 2010 Microchip Technology Inc. PIC16F/LF1826/27 Preliminary DS41391C-page 51 ...
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... R/P-1/1 — BORV STVREN R/P-1/1 U-1 U-1 — — Unimplemented bit, read as ‘1’ -n/n = Value at POR and BOR/Value at all other Resets P = Programmable bit (1) (2) Preliminary R/P-1/1 U-1 PLLEN — bit 7 R/P-1/1 R/P-1/1 WRT1 WRT0 bit 0 2010 Microchip Technology Inc. ...
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... See Section 11.5 “User ID, Device ID and Configuration Word Access” for more information on accessing these memory locations. For more information on checksum calculation, see the “PIC16F/LF1826/27 Memory Programming Specification” (DS41390). 2010 Microchip Technology Inc. PIC16F/LF1826/27 “Write Preliminary DS41391C-page 53 ...
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... W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 13-5 DEV<8:0>: Device ID bits 100111100 = PIC16F1826 100111101 = PIC16F1827 101000100 = PIC16LF1826 101000101 = PIC16LF1827 bit 4-0 REV<4:0>: Revision ID bits These bits are used to identify the revision. Note 1: This location cannot be written. DS41391C-page 54 (1) R/P-1 ...
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... XT, HS modes) and switch automatically to the internal oscillator. • Oscillator Start-up Timer (OST) ensures stability of crystal oscillator sources 2010 Microchip Technology Inc. PIC16F/LF1826/27 The oscillator module can be configured in one of eight clock modes. 1. ECL – External Clock Low Power mode (0 MHz to 0 ...
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... WDT, PWRT, Fail-Safe Clock Monitor Two-Speed Start-up and other modules Preliminary Sleep CPU and T1OSC Peripherals Clock Control FOSC<2:0> SCS<1:0> Clock Source Option for other modules 2010 Microchip Technology Inc. ...
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... Configuration Word 1: • High-power, 4-32 MHz (FOSC = 111) • Medium power, 0.5-4 MHz (FOSC = 110) • Low-power, 0-0.5 MHz (FOSC = 101) 2010 Microchip Technology Inc. PIC16F/LF1826/27 The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep ...
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... SPLLEN is ignored. Preliminary CERAMIC RESONATOR OPERATION ( MODE) ® PIC MCU OSC1/CLKIN To Internal Logic P (3) R (2) R Sleep F OSC2/CLKOUT S ( may be required for S varies with the Oscillator mode F P Oscillator Start-up Timer (OST) 4X PLL Specifications in Section 29.0 2010 Microchip Technology Inc. ) ...
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... MS1V-T1K 32.768 kHz Tuning Fork Crystal to a PIC16F690/SS” (DS91097) • AN1288, “Design Practices for Low-Power External Oscillators” (DS01288) 2010 Microchip Technology Inc. PIC16F/LF1826/27 5.2.1.6 The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required ...
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... FOSC<2:0> = 100, or • Set the System Clock Source (SCS) bits of the OSCCON register to ‘1x’ The Medium Frequency Internal Oscillator Ready bit (MFIOFR) of the OSCSTAT register indicates when the MFINTOSC is running and can be utilized. Preliminary Internal Oscillator 2010 Microchip Technology Inc. ...
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... Watchdog Timer (WDT) • Fail-Safe Clock Monitor (FSCM) The Low Frequency Internal Oscillator Ready bit (LFIOFR) of the OSCSTAT register indicates when the LFINTOSC is running and can be utilized. 2010 Microchip Technology Inc. PIC16F/LF1826/27 5.2.2.5 Internal Oscillator Frequency Selection The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits IRCF< ...
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... If the internal oscillator speed is switched between two clocks of the same source, there is no start-up delay before the new frequency is selected. Clock switching time delays are shown in Table 5-1. Start-up delay specifications are located in the oscillator tables of Specifications”. Preliminary 2010 Microchip Technology Inc. Section 29.0 “Electrical ...
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... IRCF <3:0> System Clock LFINTOSC HFINTOSC/MFINTOSC LFINTOSC Start-up Time HFINTOSC/ MFINTOSC IRCF <3:0> System Clock 2010 Microchip Technology Inc. PIC16F/LF1826/27 Start-up Time 2-cycle Sync 0 2-cycle Sync LFINTOSC turns off unless WDT or FSCM is enabled 2-cycle Sync ...
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... The Timer1 Oscillator Ready (T1OSCR) bit of the OSCSTAT register indicates whether the Timer1 oscillator is ready to be used. After the T1OSCR bit is set, the SCS bits can be configured to select the Timer1 oscillator. Preliminary 2010 Microchip Technology Inc. ...
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... Any clock source LFINTOSC Any clock source Timer1 Oscillator PLL inactive PLL active Note 1: PLL inactive. 2010 Microchip Technology Inc. PIC16F/LF1826/27 5.4.1 TWO-SPEED START-UP MODE CONFIGURATION Two-Speed Start-up mode is configured by the following settings: • IESO (of the Configuration Word Inter- nal/External Switchover bit (Two-Speed Start-up mode enabled). • ...
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... CHECKING TWO-SPEED CLOCK STATUS Checking the state of the OSTS bit of the OSCSTAT register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Word 1, or the internal oscillator Preliminary 2010 Microchip Technology Inc. ...
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... The internal clock source chosen by the FSCM is determined by the IRCF<3:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs. 2010 Microchip Technology Inc. PIC16F/LF1826/27 5.5.3 FAIL-SAFE CONDITION CLEARING The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or changing the SCS bits of the OSCCON register ...
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... Clock Monitor Output (Q) OSCFIF Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. DS41391C-page 68 Oscillator Failure Test Test Preliminary Failure Detected Test 2010 Microchip Technology Inc. ...
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... SCS<1:0>: System Clock Select bits 1x = Internal oscillator block 01 = Timer1 oscillator 00 = Clock determined by FOSC<2:0> in Configuration Word 1. Note 1: Duplicate frequency derived from HFINTOSC. 2010 Microchip Technology Inc. PIC16F/LF1826/27 R/W-1/1 R/W-1/1 IRCF<3:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
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... HFINTOSC is at least 0.5% accurate 0 = HFINTOSC is not 0.5% accurate DS41391C-page 70 R-0/q R-0/q R-q/q HFIOFR HFIOFL MFIOFR U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets q = Conditional Preliminary R-0/0 R-0/q LFIOFR HFIOFS bit 0 2010 Microchip Technology Inc. ...
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... CONFIG1 7:0 CP MCLRE Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by clock sources. 2010 Microchip Technology Inc. PIC16F/LF1826/27 R/W-0/0 R/W-0/0 R/W-0/0 TUN<5:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
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... PIC16F/LF1826/27 NOTES: DS41391C-page 72 Preliminary 2010 Microchip Technology Inc. ...
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... Upon any device Reset, the reference clock module is disabled. The user's firmware is responsible for initializing the module before enabling the output. The registers are reset to their default values. 2009 Microchip Technology Inc. PIC16F/LF1826/27 6.3 Conflicts with the CLKR pin There are two cases when the reference clock output signal cannot be output to the CLKR pin, if: • ...
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... DS41391C-page 74 R/W-1/1 R/W-0/0 R/W-0/0 CLKRDC<1:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (3) (1) (2) /4. See Section 6.3 “Conflicts with the CLKR pin” for details. Preliminary R/W-0/0 R/W-0/0 CLKRDIV<2:0> bit 0 2009 Microchip Technology Inc. ...
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... Bit -/7 Bit -/6 13:8 — — CONFIG1 7:0 CP MCLRE Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by reference clock sources. 2009 Microchip Technology Inc. PIC16F/LF1826/27 Bit 5 Bit 4 Bit 3 Bit 2 CLKRDC0 CLKRDIV2 Bit 13/5 Bit 12/4 Bit 11/3 ...
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... PIC16F/LF1826/27 NOTES: DS41391C-page 76 Preliminary 2009 Microchip Technology Inc. ...
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... SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Programming Mode Exit RESET Instruction Stack Overflow/Underflow Reset Stack Pointer External Reset MCLRE MCLR Sleep WDT Time-out Power-on Reset V DD Brown-out Reset BOR Enable 2010 Microchip Technology Inc. PIC16F/LF1826/27 PWRT Zero 64 ms LFINTOSC PWRTEN Preliminary Device Reset DS41391C-page 77 ...
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... BOR protection is unchanged by Sleep. DD Preliminary falls below V for a DD BOR , the device BORDC Device Device Operation upon Operation upon wake- up from release of POR Sleep (1) Waits for BOR ready Waits for BOR ready Begins immediately Begins immediately Begins immediately level. DD 2010 Microchip Technology Inc. ...
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... If BOREN <1:0> in Configuration Word BOR Enabled 0 = BOR Disabled bit 6-1 Unimplemented: Read as ‘0’ bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit 1 = The Brown-out Reset circuit is active 0 = The Brown-out Reset circuit is inactive 2010 Microchip Technology Inc. PIC16F/LF1826/27 T BORRDY BOR Protection Active (1) T PWRT < T ...
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... Power-up Timer and oscillator start- up timer will expire. Upon bringing MCLR high, the device will begin execution immediately (see Figure 7- 4). This is useful for testing purposes or to synchronize more than one device operating in parallel. Preliminary 2010 Microchip Technology Inc. ...
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... FIGURE 7-4: RESET START-UP SEQUENCE V DD Internal POR Power-Up Timer MCLR Internal RESET Oscillator Modes External Crystal Oscillator Start-Up Timer Oscillator F OSC Internal Oscillator Oscillator F OSC External Clock (EC) CLKIN F OSC 2010 Microchip Technology Inc. PIC16F/LF1826/27 T PWRT T MCLR T OST Preliminary DS41391C-page 81 ...
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... Program Counter 0000h ---1 1000 0000h ---u uuuu 0000h ---1 0uuu 0000h ---0 uuuu ---0 0uuu 0000h ---1 1uuu ( ---1 0uuu 0000h ---u uuuu 0000h ---u uuuu 0000h ---u uuuu Preliminary Condition STATUS PCON Register Register 00-- 110x uu-- 0uuu uu-- 0uuu uu-- uuuu uu-- uuuu 00-- 11u0 uu-- uuuu uu-- u0uu 1u-- uuuu u1-- uuuu 2010 Microchip Technology Inc. ...
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... A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) 2010 Microchip Technology Inc. PIC16F/LF1826/27 U-0 R/W/HC-1/q R/W/HC-1/q — ...
Page 84
... Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. DS41391C-page 84 Bit 5 Bit 4 Bit 3 Bit 2 — — — — — — RMCLR RI — Preliminary Register Bit 1 Bit 0 on Page — BORRDY 79 POR BOR 105 2010 Microchip Technology Inc. ...
Page 85
... A block diagram of the interrupt logic is shown in Figure 8-1 and Figure 8-2. FIGURE 8-1: INTERRUPT LOGIC TMR0IF TMR0IE From Peripheral Interrupt Logic (Figure 8-2) 2010 Microchip Technology Inc. PIC16F/LF1826/27 Wake-up (If in Sleep mode) INTF INTE IOCIF IOCIE PEIE GIE ...
Page 86
... OSFIE C2IF C2IE C1IF C1IE EEIF EEIE BCL1IF BCL1IE (1) CCP2IF (1) CCP2IE (1) CCP4IF (1) CCP4IE (1) CCP3IF (1) CCP3IE (1) TMR6IF (1) TMR6IE (1) TMR4IF (1) TMR4IE (1) BCL2IF (1) BCL2IE (1) SSP2IF (1) SSP2IE Note 1: These interrupts are available on PIC16F/LF1827 only DS41391C-page 86 Preliminary 2010 Microchip Technology Inc. To Interrupt Logic (Figure 5-1) ...
Page 87
... All interrupts will be ignored while the GIE bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again. 2010 Microchip Technology Inc. PIC16F/LF1826/27 8.2 Interrupt Latency Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins ...
Page 88
... Inst(PC) NOP NOP PC+1/FSR New PC/ 0004h ADDR PC+1 Inst(PC) NOP NOP PC+1 PC+2 INST(PC) NOP NOP PC+1 PC+2 INST(PC) NOP NOP Preliminary 0005h Inst(0004h) 0005h Inst(0004h) 0004h 0005h NOP Inst(0004h) Inst(0005h) 0004h 0005h NOP NOP Inst(0004h) 2010 Microchip Technology Inc. ...
Page 89
... Latency is the same whether Inst (PC single cycle or a 2-cycle instruction. 3: CLKOUT not available in all oscillator modes. 4: For minimum width of INT pulse, refer to AC specifications in Section 29.0 “Electrical Specifications”. 5: INTF is enabled to be set any time during the Q4-Q1 cycles. 2010 Microchip Technology Inc. PIC16F/LF1826/ ...
Page 90
... Shadow register should be modified and the value will be restored when exiting the ISR. The Shadow registers are available in Bank 31 and are readable and writable. Depending on the user’s appli- cation, other registers may also need to be saved. DS41391C-page 90 Preliminary 2010 Microchip Technology Inc. ...
Page 91
... None of the interrupt-on-change pins have changed state Note 1: The IOCIF Flag bit is read only and cleared when all the interrupt-on-change flags in the IOCBF register have been cleared by software. 2010 Microchip Technology Inc. PIC16F/LF1826/27 Note: Interrupt flag bits are set when an interrupt ...
Page 92
... Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. R/W-0/0 R/W-0/0 R/W-0/0 TXIE SSP1IE CCP1IE U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 TMR2IE TMR1IE bit 0 2010 Microchip Technology Inc. ...
Page 93
... Unimplemented: Read as ‘0’ bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt Note 1: PIC16F/LF1827 only. 2010 Microchip Technology Inc. PIC16F/LF1826/27 Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. R/W-0/0 R/W-0/0 ...
Page 94
... Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. R/W-0/0 R/W-0/0 U-0 CCP3IE TMR6IE — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary (1) R/W-0/0 U-0 TMR4IE — bit 0 2010 Microchip Technology Inc. ...
Page 95
... SSP2IE: Master Synchronous Serial Port 2 (MSSP2) Interrupt Enable bit 1 = Enables the MSSP2 interrupt 0 = Disables the MSSP2 interrupt Note 1: This register is only available on PIC16F/LF1827. 2010 Microchip Technology Inc. PIC16F/LF1826/27 Note 1: The PIE4 register is available only on the PIC16F/LF1827 device. 2: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt ...
Page 96
... R-0/0 R/W-0/0 R/W-0/0 TXIF SSP1IF CCP1IF U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary 2010 Microchip Technology Inc. should ensure the R/W-0/0 R/W-0/0 TMR2IF TMR1IF bit 0 ...
Page 97
... CCP2IF: CCP2 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending Note 1: PIC16F/LF1827 only. 2010 Microchip Technology Inc. PIC16F/LF1826/27 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register. ...
Page 98
... User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. R/W-0/0 R/W-0/0 U-0 CCP3IF TMR6IF — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary (1) R/W-0/0 U-0 TMR4IF — bit 0 2010 Microchip Technology Inc. ...
Page 99
... Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by Interrupts. Note 1: PIC16F/LF1827 only. 2010 Microchip Technology Inc. PIC16F/LF1826/27 Note 1: The PIR4 register is available only on the PIC16F/LF1827 device. 2: Interrupt flag bits are set when an inter- rupt condition occurs, regardless of the ...
Page 100
... PIC16F/LF1826/27 NOTES: DS41391C-page 100 Preliminary 2010 Microchip Technology Inc. ...
Page 101
... Section 16.0 “Digital-to-Analog Converter (DAC) Module” and Section 14.0 “Fixed Voltage Reference (FVR)” for more information on these modules. 2010 Microchip Technology Inc. PIC16F/LF1826/27 9.1 Wake-up from Sleep The device can wake-up from Sleep through one of the following events: 1 ...
Page 102
... Inst(0005h) Dummy Cycle Inst(0004h) Register on Bit 1 Bit 0 Page INTF IOCIF 91 IOCBF1 IOCBF0 134 IOCBN1 IOCBN0 134 IOCBP1 IOCBP0 134 TMR2IE TMR1IE 92 (1) — CCP2IE 93 BCL2IE SSP2IE 95 TMR2IF TMR1IF 96 (1) — CCP2IF 97 BCL2IF SSP2IF WDTPS0 SWDTEN 105 2010 Microchip Technology Inc. ...
Page 103
... Configurable time-out period is from 256 seconds (typical) • Multiple Reset conditions • Operation during Sleep FIGURE 10-1: WATCHDOG TIMER BLOCK DIAGRAM WDTE<1:0> SWDTEN WDTE<1:0> WDTE<1:0> Sleep 2010 Microchip Technology Inc. PIC16F/LF1826/27 23-bit Programmable LFINTOSC Prescaler WDT WDTPS<4:0> Preliminary WDT Time-out DS41391C-page 103 ...
Page 104
... The TO and PD bits in the STATUS register are changed to indicate the Active event. See Section 3.0 “Memory Organization” for Active more information. Disabled Active Disabled Disabled Preliminary WDT Cleared Cleared until the end of OST Unaffected 2010 Microchip Technology Inc. ...
Page 105
... SWDTEN: Software Enable/Disable for Watchdog Timer bit If WDTE<1:0> = 00: This bit is ignored. If WDTE<1:0> WDT is turned WDT is turned off If WDTE<1:0> = 1x: This bit is ignored. 2010 Microchip Technology Inc. PIC16F/LF1826/27 R/W-1/1 R/W-0/0 R/W-1/1 WDTPS<4:0> Unimplemented bit, read as ‘0’ -m/n = Value at POR and BOR/Value at all other Resets ...
Page 106
... PIC16F/LF1826/27 NOTES: DS41391C-page 106 Preliminary 2010 Microchip Technology Inc. ...
Page 107
... When code-protected, the CPU may continue to read and write the data EEPROM memory and Flash program memory. 2010 Microchip Technology Inc. PIC16F/LF1826/27 11.1 EEADRL and EEADRH Registers The EEADRH:EEADRL register pair can address maximum of 256 bytes of data EEPROM maximum of 32K words of program memory ...
Page 108
... CPU is able to read and write data to the data EEPROM recommended to code-protect the pro- gram memory when code-protecting data memory. This prevents anyone from replacing your program with a program that will access the contents of the data EEPROM. Preliminary 2010 Microchip Technology Inc. ...
Page 109
... FLASH PROGRAM MEMORY READ CYCLE EXECUTION Flash ADDR Flash Data INSTR (PC) INSTR( BSF EECON1,RD executed here executed here RD bit EEDATH EEDATL Register EERHLT 2010 Microchip Technology Inc. PIC16F/LF1826/27 EEADRH,EEADRL PC+3 INSTR ( EEDATH,EEDATL INSTR ( INSTR( Forced NOP executed here executed here Preliminary INSTR ( ...
Page 110
... NOPs. This prevents the user from executing a two-cycle instruction after the RD bit is set. 2: Flash program memory can be read regardless of the setting of the CP bit. Number of Boundary 32 words, EEADRL<4:0> = 00000 Preliminary instruction on the next 2010 Microchip Technology Inc. ...
Page 111
... NOP ; Executed (Figure 11-1) NOP ; Ignored (Figure 11-1) BSF INTCON,GIE ; Restore interrupts MOVF EEDATL,W ; Get LSB of word MOVWF PROG_DATA_LO ; Store in user location MOVF EEDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location 2010 Microchip Technology Inc. PIC16F/LF1826/27 Preliminary DS41391C-page 111 ...
Page 112
... Note: If the number of write latches is smaller than the erase block size, the code sequence provided in Example 11-5 must be repeated multiple times to fully program an erased program memory row. Preliminary 2010 Microchip Technology Inc. ...
Page 113
... EEADRL<4:0> = 00000 EEADRL<4:0> = 00001 Buffer Register 2010 Microchip Technology Inc. PIC16F/LF1826/27 continue to run. The processor does not stall when LWLO = 1, loading the write latches. After the write cycle, the processor will resume operation with the third instruction after the EECON1 write instruction. ...
Page 114
... Write AAh ; Set WR bit to begin erase ; Any instructions here are ignored as processor ; halts to begin erase sequence ; Processor will stop here and wait for erase complete. ; after erase processor continues with 3rd instruction ; Disable writes ; Enable interrupts Preliminary 2010 Microchip Technology Inc. ...
Page 115
... EECON2 MOVLW 0AAh MOVWF EECON2 BSF EECON1,WR NOP NOP BCF EECON1,WREN BSF INTCON,GIE 2010 Microchip Technology Inc. PIC16F/LF1826/27 ; Disable ints so required sequences will execute properly ; Bank 3 ; Load initial address ; ; ; ; Load initial data address ; ; ; Point to program memory ; Not configuration space ; Enable writes ...
Page 116
... Different access may exist for reads and writes. Refer to Table 11-2. When read access is initiated on an address outside the parameters listed in Table 11-2, the EEDATH:EED- ATL register pair is cleared. Function Read Access User IDs Yes Yes Yes Preliminary Write Access Yes No No 2010 Microchip Technology Inc. ...
Page 117
... EEPROM WRITE VERIFY BANKSEL EEDATL ; MOVF EEDATL, W ;EEDATL not changed ;from previous write BSF EECON1, RD ;YES, Read the ;value written XORWF EEDATL BTFSS STATUS, Z ;Is data the same GOTO WRITE_ERR ;No, handle error : ;Yes, continue 2010 Microchip Technology Inc. PIC16F/LF1826/27 Preliminary DS41391C-page 117 ...
Page 118
... Value at POR and BOR/Value at all other Resets R/W-0/0 R/W-0/0 R/W-0/0 EEADR<14:8> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-x/u R/W-x/u bit 0 R/W-x/u R/W-x/u bit 0 R/W-0/0 R/W-0/0 bit 0 R/W-0/0 R/W-0/0 bit 0 2010 Microchip Technology Inc. ...
Page 119
... RD: Read Control bit 1 = Initiates an program Flash or data EEPROM read. Read takes one cycle cleared in hardware. The RD bit can only be set (not cleared) in software Does not initiate a program Flash or data EEPROM data read. 2010 Microchip Technology Inc. PIC16F/LF1826/27 R/W/HC-0/0 R/W-x/q R/W-0/0 ...
Page 120
... Bit 3 Bit 2 FREE WRERR WREN INTE IOCIE TMR0IF EEIE BCL1IE — EEIF BCL1IF — Preliminary W-0/0 W-0/0 bit 0 Register Bit 1 Bit 0 on Page WR RD 119 107* 118 118 118 118 INTF IOCIF 91 — CCP2IE 93 — CCP2IF 97 2010 Microchip Technology Inc. ...
Page 121
... Write PORTx CK Data Register Data Bus Read PORTx To peripherals ANSELx 2010 Microchip Technology Inc. PIC16F/LF1826/27 12.1 Alternate Pin Function The Alternate Pin Function Control (APFCON0 and APFCON1) registers are used to steer specific peripheral input and output functions between different pins. The APFCON0 and APFCON1 registers are shown in Register 12-1 and Register 12-2 ...
Page 122
... Value at POR and BOR/Value at all other Resets U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 P1CSEL CCP1SEL bit 0 U-0 R/W-0/0 — TXCKSEL bit 0 2010 Microchip Technology Inc. ...
Page 123
... Register 12-6). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-up is disabled on a Power-on Reset by the WPUEN bit of the OPTION register. 2010 Microchip Technology Inc. PIC16F/LF1826/27 12.2.2 ANSELA REGISTER The ANSELA register (Register 12-7) is used to configure the Input mode of an I/O pin to analog ...
Page 124
... R/W-x/u R/W-x/u R/W-x/u LATA4 LATA3 LATA2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) (1) Preliminary R/W-x/x R/W-x/x RA1 RA0 bit 0 R/W-1/1 R/W-1/1 TRISA1 TRISA0 bit 0 R/W-x/u R/W-x/u LATA1 LATA0 bit 0 2010 Microchip Technology Inc. ...
Page 125
... Digital I/O. Pin is assigned to port or digital special function Analog input. Pin is assigned as analog input Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. 2010 Microchip Technology Inc. PIC16F/LF1826/27 U-0 U-0 U-0 — ...
Page 126
... C2OUT (Comparator) 5. RA4 DS41391C-page 126 RA5 Input only pin. RA6 1. OSC2 (enabled by Configuration Word) 2. CLKOUT 3. CLKR 4. SDO1 5. P1D 6. P2B (PIC16F/LF1827 only) 7. RA6 RA7 1. OSC1/CLKIN (enabled by Configuration Word) 2. P1C 3. CCP2 (PIC16F/LF1827 only) 4. P2A (PIC16F/LF1827 only) 5. RA7 Preliminary 2010 Microchip Technology Inc. ...
Page 127
... Name Bits Bit -/7 Bit -/6 13:8 — — CONFIG1 7:0 CP MCLRE Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA. 2010 Microchip Technology Inc. PIC16F/LF1826/27 Bit 5 Bit 4 Bit 3 Bit 2 — ANSA4 ANSA3 ANSA2 LATA4 LATA3 LATA2 — ...
Page 128
... TRISB register are maintained set when using them as analog inputs. I/O pins configured as analog input always read ‘0’. Note: The ANSELB register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read ‘0’. Section 13.0 Preliminary 2010 Microchip Technology Inc. ...
Page 129
... Bit is cleared bit 7-0 LATB<7:0>: PORTB Output Latch Value bits Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is return of actual I/O pin values. 2010 Microchip Technology Inc. PIC16F/LF1826/27 R/W-x/x R/W-x/x R/W-x/x RB4 RB3 RB2 U = Unimplemented bit, read as ‘ ...
Page 130
... Value at POR and BOR/Value at all other Resets R/W-1/1 R/W-1/1 R/W-1/1 ANSB4 ANSB3 ANSB2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) . Digital input buffer disabled. Preliminary R/W-1/1 R/W-1/1 WPUB1 WPUB0 bit 0 R/W-1/1 U-0 ANSB1 — bit 0 2010 Microchip Technology Inc. ...
Page 131
... RB0 1. P1A 2. RB0 RB1 1. SDA1 2. RX/DT 3. RB1 RB2 1. SDA2 (PIC16F/LF1827 only) 2. TX/CK 3. RX/DT 4. SDO1 5. RB2 2010 Microchip Technology Inc. PIC16F/LF1826/27 RB3 1. MDOUT 2. CCP1/P1A 3. RB3 RB4 1. SCL1 2. SCK1 3. RB4 RB5 1. SCL2 (PIC16F/LF1827 only) 2. TX/CK 3. SCK2 (PIC16F/LF1827 only) 4. P1B 5 ...
Page 132
... TRISB4 TRISB3 WPUB5 WPUB4 WPUB3 Preliminary Register Bit 2 Bit 1 Bit 0 on Page ANSB2 ANSB1 — 130 LATB2 LATB1 LATB0 129 PS2 PS1 PS0 177 RB2 RB1 RB0 129 TRISB2 TRISB1 TRISB0 129 WPUB2 WPUB1 WPUB0 130 2010 Microchip Technology Inc. ...
Page 133
... R RBx IOCBPx 2010 Microchip Technology Inc. PIC16F/LF1826/27 13.3 Interrupt Flags The IOCBFx bits located in the IOCBF register are status flags that correspond to the Interrupt-on-change pins of the port expected edge is detected on an appropriately enabled pin, then the status flag for that pin will be set, and an interrupt will be generated if the IOCIE interrupt ...
Page 134
... R/W/HS-0/0 IOCBF4 IOCBF3 IOCBF2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets HS - Bit is set in hardware Preliminary R/W-0/0 R/W-0/0 IOCBP1 IOCBP0 bit 0 R/W-0/0 R/W-0/0 IOCBN1 IOCBN0 bit 0 R/W/HS-0/0 R/W/HS-0/0 IOCBF1 IOCBF0 bit 0 2010 Microchip Technology Inc. ...
Page 135
... IOCBF7 IOCBF6 IOCBN IOCBN7 IOCBN6 IOCBP IOCBP7 IOCBP6 TRISB TRISB7 TRISB6 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by interrupt-on-change. 2010 Microchip Technology Inc. PIC16F/LF1826/27 Bit 5 Bit 4 Bit 3 Bit 2 ANSB5 ANSB4 ANSB3 ANSB2 TMR0IE INTE IOCIE ...
Page 136
... PIC16F/LF1826/27 NOTES: DS41391C-page 136 Preliminary 2010 Microchip Technology Inc. ...
Page 137
... FVRCON register. FIGURE 14-1: VOLTAGE REFERENCE BLOCK DIAGRAM ADFVR<1:0> CDAFVR<1:0> FVREN FVRRDY 2009 Microchip Technology Inc. PIC16F/LF1826/27 14.1 Independent Gain Amplifiers The output of the FVR supplied to the ADC, Comparators, and DAC is routed through two independent programmable gain amplifiers. Each , with 1 ...
Page 138
... U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets q = Value depends on condition ( Bit 5 Bit 4 Bit 3 Bit 2 Reserved Reserved CDAFVR1 CDAFVR0 Preliminary R/W-0/0 R/W-0/0 ADFVR<1:0> bit 0 (2) (2) (2) (2) Register Bit 1 Bit 0 on page ADFVR1 ADFVR0 138 2009 Microchip Technology Inc. ...
Page 139
... AN10 AN11 DAC FVR Buffer1 CHS<4:0> Note: When ADON = 0, all multiplexer inputs are disconnected. 2010 Microchip Technology Inc. PIC16F/LF1826/27 The ADC voltage reference is software selectable to be either internally generated or externally supplied. The ADC can generate an interrupt upon completion of (ADC) allows a conversion ...
Page 140
... Section 29.0 “Electrical Specifications” for more information. Table 15-1 gives examples of appropriate ADC clock selections. Note: Unless using the F system clock frequency will change the ADC adversely affect the ADC result. Preliminary peri- AD specification AD , any changes in the RC clock frequency, which may 2010 Microchip Technology Inc. ...
Page 141
... Sleep mode. FIGURE 15-2: ANALOG-TO-DIGITAL CONVERSION Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit 2010 Microchip Technology Inc. PIC16F/LF1826/ DEVICE OPERATING FREQUENCIES AD S Device Frequency (F 20 MHz 16 MHz (2) (2) (2) 100 ns 125 ns (2) (2) (2) 200 ns 250 ns ...
Page 142
... ADCON1 register controls the output format. Figure 15-3 shows the two output formats. ADRESH LSB bit 0 bit 7 10-bit A/D Result MSB bit 0 bit 7 10-bit A/D Result Preliminary ADRESL bit 0 Unimplemented: Read as ‘0’ LSB bit 0 2010 Microchip Technology Inc. ...
Page 143
... Note: A device Reset forces all registers to their Reset state. Thus, the ADC module is turned off and any pending conversion is terminated. 2010 Microchip Technology Inc. PIC16F/LF1826/27 15.2.4 ADC OPERATION DURING SLEEP The ADC module can operate during Sleep. This requires the ADC clock source to be set to the F option ...
Page 144
... MOVF ADRESL,W MOVWF RESULTLO Preliminary A/D CONVERSION ; ;clock ;Vdd and Vss Vref ; ;Set RA0 to input ; ;Set RA0 to analog ; ;Turn ADC On ;Acquisiton delay ;No, test again ; ;Read upper 2 bits ;store in GPR space ; ;Read lower 8 bits ;Store in GPR space 2010 Microchip Technology Inc. ...
Page 145
... ADC is enabled 0 = ADC is disabled and consumes no operating current Note 1: See Section 16.0 “Digital-to-Analog Converter (DAC) Module” for more information. 2: See Section 14.0 “Fixed Voltage Reference (FVR)” for more information. 2010 Microchip Technology Inc. PIC16F/LF1826/27 R/W-0/0 R/W-0/0 R/W-0/0 CHS<4:0> ...
Page 146
... R/W-0/0 — ADNREF U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets SS (1) - pin REF DD (1) + pin REF + pin as the source of the positive reference, be aware that a REF Preliminary R/W-0/0 R/W-0/0 ADPREF<1:0> bit 0 2010 Microchip Technology Inc. ...
Page 147
... Bit is set ‘0’ = Bit is cleared bit 7-6 ADRES<1:0>: ADC Result Register bits Lower 2 bits of 10-bit conversion result bit 5-0 Reserved: Do not use. 2010 Microchip Technology Inc. PIC16F/LF1826/27 R/W-x/u R/W-x/u R/W-x/u ADRES<9:2> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
Page 148
... U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets R/W-x/u R/W-x/u R/W-x/u ADRES<7:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-x/u R/W-x/u ADRES<9:8> bit 0 R/W-x/u R/W-x/u bit 0 2010 Microchip Technology Inc. ...
Page 149
... REF 2: The charge holding capacitor (C 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification. 2010 Microchip Technology Inc. PIC16F/LF1826/27 source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an A/D acquisition must be done before the conversion can be started ...
Page 150
... V - REF DS41391C-page 150 V DD Sampling Switch 0. Rss R IC LEAKAGE (1) I 0. Full-Scale Range 0.5 LSB Zero-Scale Full-Scale Transition V REF Transition Preliminary HOLD REF Sampling Switch (k) Analog Input Voltage 1.5 LSB + 2010 Microchip Technology Inc. ...
Page 151
... TRISB6 FVRCON FVREN FVRRDY DACCON0 DACEN DACLPS DACCON1 — — Legend: — = unimplemented read as ‘0’. Shaded cells are not used for ADC module. 2010 Microchip Technology Inc. PIC16F/LF1826/27 Bit 5 Bit 4 Bit 3 Bit 2 CHS3 CHS2 CHS1 CHS0 ADCS1 ADCS0 — ...
Page 152
... PIC16F/LF1826/27 NOTES: DS41391C-page 152 Preliminary 2010 Microchip Technology Inc. ...
Page 153
... SRC The negative voltage source is disabled by setting the DACLPS bit in the DACCON0 register. Clearing the DACLPS bit in the DACCON0 register disables the positive voltage source. 2009 Microchip Technology Inc. PIC16F/LF1826/27 16.3.1 OUTPUT CLAMPED TO POSITIVE VOLTAGE SOURCE The DAC output voltage can be set to V ...
Page 154
... Output Clamped to Positive Voltage Source V + SRC R DACR<4:0> = 11111 R DACEN = 0 DACLPS = 1 DAC Voltage Ladder (see Figure 16- SRC DS41391C-page 154 Output Clamped to Negative Voltage Source V + SRC R R DACEN = 0 DACLPS = SRC Preliminary 2009 Microchip Technology Inc. DAC Voltage Ladder (see Figure 16-2) DACR<4:0> = 00000 ...
Page 155
... V - REF V SS 2009 Microchip Technology Inc. PIC16F/LF1826/27 digital input threshold detector functions of that pin. Reading the DACOUT pin when it has been configured for DAC reference voltage output will always return a ‘0’. Due to the limited current drive capability, a buffer must be used on the DAC voltage reference output for external connections to DACOUT ...
Page 156
... Effects of a Reset A device Reset affects the following: • DAC is disabled. • DAC output voltage is removed from the DACOUT pin. • The DACR<4:0> range select bits are cleared. DS41391C-page 156 + DACOUT – Preliminary Buffered DAC Output 2009 Microchip Technology Inc. ...
Page 157
... OUT SRC SRC Note 1: The output select bits are always right justified to ensure that any number of bits can be used without affecting the register layout. 2009 Microchip Technology Inc. PIC16F/LF1826/27 U-0 R/W-0/0 R/W-0/0 — DACPSS<1:0> Unimplemented bit, read as ‘0’ ...
Page 158
... Shaded cells are unused with the DAC module. DS41391C-page 158 Bit 5 Bit 4 Bit 3 Bit 2 Reserved Reserved CDAFVR1 CDAFVR0 DACOE — DACPSS1 DACPSS0 — DACR4 DACR3 DACR2 Preliminary Register Bit 1 Bit 0 on page ADFVR1 ADFVR0 138 — DACNSS 157 DACR1 DACR0 157 2009 Microchip Technology Inc. ...
Page 159
... Note: Enabling both the Set and Reset inputs from any one source at the same time may result in indeterminate operation, as the Reset dominance cannot be assured. 2010 Microchip Technology Inc. PIC16F/LF1826/27 17.2 Latch Output The SRQEN and SRNQEN bits of the SRCON0 regis- ter control the Q and Q latch outputs ...
Page 160
... SRRPE SRCLK SRRCKE (3) SYNCC2OUT SRRC2E (3) SYNCC1OUT SRRC1E Note and simultaneously Pulse generator causes a 1 Q-state pulse width. 3: Name denotes the connection point at the comparator output. DS41391C-page 160 SRLEN SRQEN (1) Latch R Q SRLEN SRNQEN Preliminary 2010 Microchip Technology Inc. SRQ SRNQ ...
Page 161
... Pulse set input for 1 Q-clock period effect on set input. bit 0 SRPR: Pulse Reset Input of the SR Latch bit 1 = Pulse Reset input for 1 Q-clock period effect on Reset input. Note 1: Set only, always reads back ‘0’. 2010 Microchip Technology Inc. PIC16F/LF1826/ MHz MHz OSC OSC 39 ...
Page 162
... C1 Comparator output has no effect on the Reset input of the SR latch DS41391C-page 162 R/W-0/0 R/W-0/0 R/W-0/0 SRSC1E SRRPE SRRCKE U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 SRRC2E SRRC1E bit 0 2010 Microchip Technology Inc. ...
Page 163
... SRCON0 SRLEN SRCLK2 SRCON1 SRSPE SRSCKE TRISA TRISA7 TRISA6 Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the SR latch module. 2010 Microchip Technology Inc. PIC16F/LF1826/27 Bit 5 Bit 4 Bit 3 Bit 2 — ANSA4 ANSA3 ANSA2 SRCLK1 SRCLK0 SRQEN ...
Page 164
... PIC16F/LF1826/27 NOTES: DS41391C-page 164 Preliminary 2010 Microchip Technology Inc. ...
Page 165
... V -, the output of the IN comparator is a digital low level. When the analog voltage greater than the analog voltage the output of the comparator is a digital high level. IN 2010 Microchip Technology Inc. PIC16F/LF1826/27 FIGURE 18-1: SINGLE COMPARATOR – V ...
Page 166
... DS41391C-page 166 (1) Interrupt Interrupt C POL CxHYS D (from Timer1) T1CLK Preliminary CxINTP det Set CxIF CxINTN det C OUT X To Data Bus Q MC OUT X To ECCP PWM Logic C SYNC TRIS bit C OUT Timer1 or SR Latch SYNCC OUT X 2010 Microchip Technology Inc. ...
Page 167
... FVR Buffer2 3 CxON PCH<1:0> Note 1: When CxON = 0, the Comparator will produce a ‘0’ at the output 2: When CxON = 0, all multiplexer inputs are disconnected. 3: Output of comparator can be frozen during debugging. 2010 Microchip Technology Inc. PIC16F/LF1826/27 (1) Interrupt Interrupt C POL CxHYS D (from Timer1) ...
Page 168
... CxSP control bit. The default state for this bit is ‘1’ which selects the normal speed mode. Device power consumption can be optimized at the cost of slower comparator propaga- tion delay by clearing the CxSP bit to ‘0’. Preliminary 2010 Microchip Technology Inc. CxOUT ...
Page 169
... Timer1 clock source and Timer1 increments on the rising edge of its clock source. See the Comparator Block Diagram (Figure 18-2) and the Timer1 Block Diagram (Figure 20-1) for more information. 2010 Microchip Technology Inc. PIC16F/LF1826/27 18.5 Comparator Interrupt An interrupt can be generated upon a change in the ...
Page 170
... Pins configured as digital inputs will convert as an analog input, according to the input specification. 2: Analog levels on any pin defined as a digital input, may cause the input buffer to consume more current than is specified. Preliminary 2010 Microchip Technology Inc. and V . The DD SS and V . ...
Page 171
... Input Capacitance PIN I = Leakage Current at the pin due to various junctions LEAKAGE R = Interconnect Resistance Source Impedance Analog Voltage Threshold Voltage T Note 1: See Section 29.0 “Electrical Specifications” 2010 Microchip Technology Inc. PIC16F/LF1826/ 0. (1) I LEAKAGE 0. Vss Preliminary To Comparator DS41391C-page 171 ...
Page 172
... Output updated on the falling edge of Timer1 clock source Comparator output to Timer1 and I/O pin is asynchronous. DS41391C-page 172 R/W-0/0 U-0 R/W-1/1 CxPOL CxSP — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 CxHYS CxSYNC bit 0 2010 Microchip Technology Inc. ...
Page 173
... Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1 MC2OUT: Mirror Copy of C2OUT bit bit 0 MC1OUT: Mirror Copy of C1OUT bit 2010 Microchip Technology Inc. PIC16F/LF1826/27 R/W-0/0 U-0 CxPCH<1:0> — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
Page 174
... ANSA0 125 CxHYS CxSYNC 172 CxNCH1 CxNCH0 173 MC2OUT MC1OUT 173 — DACNSS 157 DACR1 DACR0 157 ADFVR1 ADFVR0 138 INTF IOCIF 91 LATA1 LATA0 124 (1) — CCP2IE 93 (1) — CCP2IF 97 RA1 RA0 124 TRISA1 TRISA0 124 2010 Microchip Technology Inc. ...
Page 175
... From CPSCLK 1 TMR0SE TMR0CS T0XCS 2010 Microchip Technology Inc. PIC16F/LF1826/27 19.1.2 8-BIT COUNTER MODE In 8-Bit Counter mode, the Timer0 module will increment on every rising or falling edge of the T0CKI pin or the Capacitive Sensing Oscillator (CPSCLK) signal. 8-Bit Counter mode using the T0CKI pin is selected by setting the TMR0CS bit in the OPTION register to ‘ ...
Page 176
... Section 29.0 “Electrical Specifications”. 19.1.6 OPERATION DURING SLEEP Timer0 cannot operate while the processor is in Sleep mode. The contents of the TMR0 register will remain unchanged while the processor is in Sleep mode. DS41391C-page 176 Preliminary 2010 Microchip Technology Inc. ...
Page 177
... Timer0 Module Register TRISA TRISA7 TRISA6 Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by the Timer0 module. * Page provides register information. 2010 Microchip Technology Inc. PIC16F/LF1826/27 R/W-1/1 R/W-1/1 R/W-1/1 TMR0SE PSA U = Unimplemented bit, read as ‘0’ ...
Page 178
... PIC16F/LF1826/27 NOTES: DS41391C-page 178 Preliminary 2010 Microchip Technology Inc. ...
Page 179
... T1CKI Note 1: ST Buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. 2010 Microchip Technology Inc. PIC16F/LF1826/27 • Gate Toggle Mode • Gate Single-pulse Mode • Gate Value Status • Gate Event Interrupt Figure 20 block diagram of the Timer1 module ...
Page 180
... T1CKI is low. T1OSCEN System Clock ( OSC Instruction Clock (F x OSC Capacitive Sensing Oscillator x External Clocking on T1CKI Pin 0 Osc.Circuit On T1OSI/T1OSO Pins 1 Preliminary internal clock source is selected, the system clock or they can run Clock Source /4) 2010 Microchip Technology Inc. ...
Page 181
... A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMR1H:TMR1L register pair. 2010 Microchip Technology Inc. PIC16F/LF1826/27 20.6 Timer1 Gate Timer1 can be configured to count freely or the count can be enabled and disabled using Timer1 Gate circuitry ...
Page 182
... TMR1GIF flag bit in the PIR1 register will be set. If the TMR1GIE bit in the PIE1 register is set, then an interrupt will be recognized. The TMR1GIF flag bit operates even when the Timer1 Gate is not enabled (TMR1GE bit is cleared). Preliminary 2010 Microchip Technology Inc. ...
Page 183
... T1CKI = 0 when TMR1 Enabled Note 1: Arrows indicate counter increments Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. 2010 Microchip Technology Inc. PIC16F/LF1826/27 20.9 ECCP/CCP Capture/Compare Time Base The CCP modules use the TMR1H:TMR1L register pair as the time base when operating in Capture or Compare mode ...
Page 184
... PIC16F/LF1826/27 FIGURE 20-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL T1G_IN T1CKI T1GVAL Timer1 N FIGURE 20-4: TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM T1G_IN T1CKI T1GVAL Timer1 DS41391C-page 184 Preliminary 2010 Microchip Technology Inc ...
Page 185
... TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 N Cleared by software TMR1GIF 2010 Microchip Technology Inc. PIC16F/LF1826/27 Cleared by hardware on falling edge of T1GVAL Set by hardware on falling edge of T1GVAL Preliminary Cleared by software DS41391C-page 185 ...
Page 186
... TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 N Cleared by software TMR1GIF DS41391C-page 186 Set by hardware on falling edge of T1GVAL Preliminary 2010 Microchip Technology Inc. Cleared by hardware on falling edge of T1GVAL Cleared by software ...
Page 187
... This bit is ignored. Timer1 uses the internal clock when TMR1CS<1:0> = 1X. bit 1 Unimplemented: Read as ‘0’ bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Clears Timer1 Gate flip-flop 2010 Microchip Technology Inc. PIC16F/LF1826/27 R/W-0/u R/W-0/u R/W-0/u T1OSCEN T1SYNC U = Unimplemented bit, read as ‘0’ ...
Page 188
... Comparator 1 optionally synchronized output (SYNCC1OUT Comparator 2 optionally synchronized output (SYNCC2OUT) DS41391C-page 188 R/W-0/u R/W/HC-0/u R-x/x T1GSPM T1GGO/ T1GVAL DONE U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets HC = Bit is cleared by hardware Preliminary R/W-0/u R/W-0/u T1GSS<1:0> bit 0 2010 Microchip Technology Inc. ...
Page 189
... TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC T1CON TMR1GE T1GPOL T1GCON Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. * Page provides register information. 2010 Microchip Technology Inc. PIC16F/LF1826/27 Bit 5 Bit 4 Bit 3 Bit 2 ANSB5 ANSB4 ANSB3 ...
Page 190
... PIC16F/LF1826/27 NOTES: DS41391C-page 190 Preliminary 2010 Microchip Technology Inc. ...
Page 191
... Optional use as the shift clock for the MSSPx modules (Timer2 only) See Figure 21-1 for a block diagram of Timer2/4/6. FIGURE 21-1: TIMER2/4/6 BLOCK DIAGRAM Prescaler F /4 OSC 1:1, 1:4, 1:16, 1:64 2 TxCKPS<1:0> 2010 Microchip Technology Inc. PIC16F/LF1826/27 TMRx Output Reset TMRx Postscaler Comparator 1 PRx TxOUTPS< ...
Page 192
... Timer2/4/6 Operation During Sleep The Timer2/4/6 timers cannot be operated while the the output processor is in Sleep mode. The contents of the TMRx and PRx registers will remain unchanged while the processor is in Sleep mode. the 4-bit Preliminary 2010 Microchip Technology Inc. ...
Page 193
... TMRxON: Timerx On bit 1 = Timerx Timerx is off bit 1-0 TxCKPS<1:0>: Timer2-type Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler Prescaler is 64 2010 Microchip Technology Inc. PIC16F/LF1826/27 R/W-0/0 R/W-0/0 R/W-0/0 TMRxON U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary ...
Page 194
... TMR4ON TMR6ON (1) (1) Preliminary Register Bit 1 Bit 0 on Page INTF IOCIF 91 TMR2IE TMR1IE 92 TMR2IF TMR1IF 96 — TMR4IE — 94 — TMR4IF — 98 191* 191* 191* T2CKPS1 T2CKPS0 193 T4CKPS1 T4CKPS0 193 T6CKPS1 T6CKPS0 193 191* 191* 193* 2010 Microchip Technology Inc. ...
Page 195
... Reserved * No Channel * Selected 1111 2010 Microchip Technology Inc. PIC16F/LF1826/27 Using this method, the DSM can generate the following types of Key Modulation schemes: • Frequency-Shift Keying (FSK) • Phase-Shift Keying (PSK) • On-Off Keying (OOK) Additionally, the following features are provided within the DSM module: • ...
Page 196
... MDCHSYNC bit in the MDCARH register. Synchroniza- tion for the carrier low signal can be enabled by setting the MDCLSYNC bit in the MDCARL register. Figure 22-1 through Figure 22-5 show timing diagrams of using various synchronization methods. Preliminary 2010 Microchip Technology Inc. ...
Page 197
... Active Carrier State FIGURE 22-3: CARRIER HIGH SYNCHRONIZATION (MDSHSYNC = 1, MDCLSYNC = 0) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) MDCHSYNC = 1 MDCLSYNC = 0 CARH Active Carrier State 2010 Microchip Technology Inc. PIC16F/LF1826/27 CARL CARH CARH CARL both Preliminary CARL both CARL DS41391C-page 197 ...
Page 198
... Active Carrier CARH State FIGURE 22-5: FULL SYNCHRONIZATION (MDSHSYNC = 1, MDCLSYNC = 1) Carrier High (CARH) Carrier Low (CARL) Modulator (MOD) Falling edges used to sync MDCHSYNC = 1 MDCLSYNC = 1 Active Carrier CARH State DS41391C-page 198 CARL CARH CARL CARH Preliminary 2010 Microchip Technology Inc. CARL CARL ...
Page 199
... The DSM module is not affected by Sleep mode. The DSM can still operate during Sleep, if the Carrier and Modulator input sources are also still operable during Sleep. 2010 Microchip Technology Inc. PIC16F/LF1826/27 22.12 Effects of a Reset Upon any device Reset, the Data Signal Modulator module is disabled ...
Page 200
... MDBIT must be selected as the modulation source in the MDSRC register for this operation. DS41391C-page 200 R/W-0/0 R-0/0 U-0 MDOPOL MDOUT — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) Preliminary U-0 R/W-0/0 — MDBIT bit 0 (2) 2010 Microchip Technology Inc. ...