PIC24FJ64GB004-I/ML Microchip Technology, PIC24FJ64GB004-I/ML Datasheet
PIC24FJ64GB004-I/ML
Specifications of PIC24FJ64GB004-I/ML
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PIC24FJ64GB004-I/ML Summary of contents
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... This specification includes programming specifications for the following devices: • PIC24FJ32GA102 • PIC24FJ64GA102 • PIC24FJ32GA104 • PIC24FJ64GA104 • PIC24FJ32GB002 • PIC24FJ64GB002 • PIC24FJ32GB004 • PIC24FJ64GB004 2.0 PROGRAMMING OVERVIEW OF THE PIC24FJ64GA1/GB0 FAMILIES There are two methods of programming PIC24FJ64GA1/GB0 families of devices discussed in this programming specification ...
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... V SS Regulator Disabled (V tied DDCORE (1) 2.5V PIC24FJXXGA1/GB0 V DD DISVREG V /V DDCORE CAP V SS Note 1: These are typical operating voltages. Refer to Section 7.0 “AC/DC Characteristics and Timing Requirements” for the full operating ranges of V and DDCORE © 2009 Microchip Technology Inc ...
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... SS FIGURE 2-3: PIN DIAGRAMS 28-Pin PDIP, SOIC (GA1 Devices) PGED1/AN2/C2INB/RP0/CN4/RB0 PGEC1/AN3/C2INA/RP1/CN5/RB1 PGED3/ASDA1/RP5/PMD7/CN27/RB5 28-Pin QFN (GA1 Devices) PGED1/AN2/C2INB/RP0/CN4/RB0 PGEC1/AN3/C2INA/RP1/CN5/RB1 © 2009 Microchip Technology Inc. PIC24FJ64GA1/GB0 During Programming Pin Type Pin Description P Programming Enable I Disable for On-Chip Voltage Regulator P Power Supply P Ground ...
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... USB RB3 PGEC2/D-/VMIO/RP11/CN15/RB11 PGED2/D+/VPIO/RP10/CN16/RB10 RA2 CAP RA3 DISVREG 10 19 RB4 RB9 11 18 RA4 RB8 RB7 RB5 BUS RB13 USB RB2 PGEC2/D-/VMIO/RP11/CN15/RB11 3 19 PIC24FJXXGB002 RB3 PGED2/D+/VPIO/RP10/CN16/RB10 CAP DDCORE RA2 6 DISVREG 16 RA3 7 RB9 © 2009 Microchip Technology Inc. /V DDCORE ...
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... FIGURE 2-5: PIN DIAGRAMS (CONTINUED) 44-Pin TQFP, QFN (GA1 Devices) DISVREG V /V CAP DDCORE PGED2/RP10/PMD2/CN16/RB10 PGEC2/RP11/PMD1/CN15/RB11 © 2009 Microchip Technology Inc. PIC24FJ64GA1/GB0 RB9 1 RC6 2 RC7 3 RC8 4 RC9 5 PIC24FJXXGA104 RB12 10 RB13 11 RB4 33 RA8 32 RA3 31 RA2 RC2 27 RC1 26 RC0 25 RB3 24 23 RB2 DS39934B-page 5 ...
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... FIGURE 2-6: PIN DIAGRAMS (CONTINUED) 44-Pin TQFP, QFN (GB0 Devices) DISVREG V /V CAP PGED2/D+/VPIO/RP10/CN16/RB10 PGEC2/D-/VMIO/RP11/CN15/RB11 DS39934B-page 6 RB9 1 RC6 2 RC7 3 RC8 4 RC9 5 PIC24FJXXGB004 6 DDCORE USB 10 RB13 11 RB4 33 RA8 32 RA3 31 RA2 RC2 27 RC1 26 RC0 25 RB3 24 RB2 23 © 2009 Microchip Technology Inc. ...
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... PIC24FJ32GA10X 0057FEh (11K) PIC24FJ32GB00X PIC24FJ64GA10X 00ABFEh (22K) PIC24FJ64GB00X © 2009 Microchip Technology Inc. PIC24FJ64GA1/GB0 Locations, 800000h through 8007FEh, are reserved for executive code memory. This region stores the programming executive and the debugging executive. The programming executive is used for device programming and the debugging executive is used for in-circuit debugging ...
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... Flash Configuration Words (1) 0XXXFEh (1) 0XXX00h Reserved 7FFFFEh 800000h Executive Code Memory (1024 x 24-bit) 8007FEh 800800h Reserved 80087Eh 800880h Diagnostic and Calibration Words (8 x 24-bit) 80088Eh 800890h Reserved FEFFFEh FF0000h Device 16-bit) FF0002h FF0004h Reserved FFFFFEh © 2009 Microchip Technology Inc. ...
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... Configuration registers. Code memory (including the Configuration registers) is then verified to ensure that programming was successful. Then, program the code-protect Configuration bits, if required. © 2009 Microchip Technology Inc. PIC24FJ64GA1/GB0 FIGURE 3-1: HIGH-LEVEL ICSP™ PROGRAMMING FLOW Start Enter ICSP™ ...
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... If the PC points to these locations, the device will reset, possibly interrupting the ICSP operation. To prevent this, instructions should be periodically executed to reset the safe space. The optimal method to accomplish this is to perform a GOTO 0x200 P4A MSB Execute 24-Bit Instruction, Fetch Next Control Code © 2009 Microchip Technology Inc. ...
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... Execute Previous Instruction, CPU Held in Idle Fetch REGOUT Control Code PGDx = Input © 2009 Microchip Technology Inc. PIC24FJ64GA1/GB0 Note 1: After the contents of VISI are shifted out, PIC24FJ64GA1/GB0 devices maintain PGDx as an output until the first rising edge of the next clock is received. ...
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... P7 has elapsed will not be interpreted as valid. . After successful entry, the program memory can be accessed and programmed in serial fashion. While in ICSP mode, all unused I/Os are placed in the high-impedance state ... b29 b28 b27 P1A P1B must be IH P19 P7 © 2009 Microchip Technology Inc. ...
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... Starting a programming cycle is performed as follows: BSET NVMCON, #WR © 2009 Microchip Technology Inc. PIC24FJ64GA1/GB0 3.5 Erasing Program Memory The procedure for erasing program memory (all of code memory, data memory, executive memory and code-protect bits) consists of setting NVMCON to 404Fh and executing the programming cycle ...
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... MOV 0000 883C22 MOV 0000 000000 NOP 0001 <VISI> Clock out contents of the VISI register. 0000 000000 NOP DS39934B-page 14 Description 0x200 #0x404F, W10 W10, NVMCON #<PAGEVAL>, W0 W0, TBLPAG #0x0000, W0 W0,[W0] NVMCON, #WR 0x200 NVMCON, W2 W2, VISI © 2009 Microchip Technology Inc. ...
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... MOV 0000 2xxxx5 MOV © 2009 Microchip Technology Inc. PIC24FJ64GA1/GB0 In Step 5, eight TBLWT instructions are used to copy the data from W0:W5 to the write latches of code memory. Since code memory is programmed 64 instruction words at a time, Steps 4 and 5 are repeated 16 times to load all the write latches (Step 6) ...
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... NOP Step 9: Reset device internal PC. 0000 040200 GOTO 0000 000000 NOP Step 10: Repeat Steps 3-9 until all code memory is programmed. DS39934B-page 16 Description W6 [W6++], [W7] [W6++], [W7++] [W6++], [++W7] [W6++], [W7++] [W6++], [W7] [W6++], [W7++] [W6++], [++W7] [W6++], [W7++] NVMCON, #WR 0x200 NVMCON, W2 W2, VISI 0x200 © 2009 Microchip Technology Inc. ...
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... FIGURE 3-7: PROGRAM CODE MEMORY FLOW LoopCount = LoopCount + 1 © 2009 Microchip Technology Inc. PIC24FJ64GA1/GB0 Start LoopCount = 0 Configure Device for Writes Load 2 Bytes to Write Buffer at <Addr> All No bytes written? Yes Start Write Sequence and Poll for WR bit to be Cleared All No locations done? ...
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... After verification is finished, the code protection bit can be programmed to a ‘0’ by using a word write to the appropriate Configuration Word. © 2009 Microchip Technology Inc. Default Value 7FFFh FFFFh FFFFh ...
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... Clock out contents of the VISI register. 0000 000000 NOP Step 9: Reset device internal PC. 0000 040200 GOTO 0000 000000 NOP Step 10: Repeat Steps 5-9 to write CW3 to CW1. © 2009 Microchip Technology Inc. PIC24FJ64GA1/GB0 Description 0x200 #<CW4Address15:0>, W7 #0x4003, W10 W10, NVMCON #<CW4Address23:16>, W0 W0, TBLPAG #<CW4_VALUE>, W6 W6, [W7++] NVMCON, #WR ...
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... VISI register, using the REGOUT command. Step 4 is repeated until the desired amount of code memory is read. Description 0x200 #<SourceAddress23:16>, W0 W0, TBLPAG #<SourceAddress15:0>, W6 #VISI, W7 [W6], [W7] [W6++], [W7++] [++W6], [W7--] [W6++], [W7] 0x200 © 2009 Microchip Technology Inc. ...
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... GOTO 0000 000000 NOP © 2009 Microchip Technology Inc. PIC24FJ64GA1/GB0 Table 3-9 shows the ICSP programming details for reading the Configuration Words. Note that the TBLPAG register must be loaded with 00h, and the Read Pointer, W6, is initialized to the lower 16 bits of the Configuration Word location ...
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... P16, should elapse between the last clock and program signals on PGCx and PGDx before removing V FIGURE 3-9: MCLR V DD PGDx Failure, Report PGCx Error EXITING ICSP™ MODE P16 P17 PGD = Input © 2009 Microchip Technology Inc. ...
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... NOP 0000 000000 NOP Step 3: Output the VISI register using the REGOUT command. 0001 <VISI> Clock out contents of the VISI register 0000 000000 NOP © 2009 Microchip Technology Inc. PIC24FJ64GA1/GB0 Description 0x200 #0x80, W0 W0, TBLPAG #0x7F0, W0 #VISI, W1 [W0], [W1] DS39934B-page 23 ...
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... Programming Executive to Memory”. Section 3.0 “Device Programming – ICSP” describes the ICSP programming method. Section 3.11 “Reading the Application ID Word” describes the procedure for reading the Application ID Word in ICSP mode. © 2009 Microchip Technology Inc. present), the ...
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... ENTERING ENHANCED ICSP™ MODE P6 P14 MCLR V DD PGDx PGCx P18 © 2009 Microchip Technology Inc. PIC24FJ64GA1/GB0 4.3 Entering Enhanced ICSP Mode As shown in Figure 4-3, entering Enhanced ICSP Program/Verify mode requires three steps: 1. The MCLR pin is briefly driven high, then low. 2. ...
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... The READP command can be used to read back all of the programmed code memory. Alternatively, you can have the programmer perform the verification after the entire device is programmed using a checksum computation. © 2009 Microchip Technology Inc. No Failure Report Error ...
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... DSBOR CW4<6> FCKSM<1:0> CW2<7:6> Note 1: Available on PIC24FJXXXGB0XX devices only. © 2009 Microchip Technology Inc. PIC24FJ64GA1/GB0 The descriptions for the Configuration bits in the Flash Configuration Words are shown in Table 4-2. Note: Although not implemented with a specific function, the bit at CW1<15> must always be maintained as ‘ ...
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... The IOLOCK bit can only be set once (provided an unlocking sequence is executed). Once IOLOCK is set, this prevents any possible future RP register changes. JTAG Enable bit 1 = JTAG enabled 0 = JTAG disabled OSC2 Pin Function bit (except in XT and HS modes OSC2 is clock output 0 = OSC2 is general purpose digital I/O pin © 2009 Microchip Technology Inc. ...
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... WPDIS CW3<13> WPEND CW3<15> Note 1: Available on PIC24FJXXXGB0XX devices only. © 2009 Microchip Technology Inc. PIC24FJ64GA1/GB0 Description USB 96 MHz PLL Prescaler Select bits 111 = Oscillator input divided by 12 (48 MHz input) 110 = Oscillator input divided by 8 (32 MHz input) 101 = Oscillator input divided by 6 (24 MHz input) ...
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... Last address of designated code page is the upper boundary of the segment. If WPEND = 0: First address of designated code page is the lower boundary of the segment. Voltage Regulator Standby Mode Wake-up Time Select bits 11 = Default regulator wake time used 01 = Fast regulator wake time used x0 = Reserved; do not use © 2009 Microchip Technology Inc. ...
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... Configuration bits. FIGURE 4-5: CONFIGURATION BIT PROGRAMMING FLOW ConfigAddress = ConfigAddress + 2 Note 1: Refer to Table 2-2 for Flash Configuration Word addresses. © 2009 Microchip Technology Inc. PIC24FJ64GA1/GB0 4.6.3 PROGRAMMING VERIFICATION After the Configuration bits are programmed, the contents of memory should be verified to ensure that the programming was successful ...
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... MCLR, as shown in Figure 4-6. The only require- ment for exit is that an interval, P16, should elapse between the last clock and program signals on PGCx and PGDx before removing FIGURE 4-6: EXITING ENHANCED ICSP™ MODE P16 P17 V IH MCLR PGDx PGCx PGDx = Input © 2009 Microchip Technology Inc. IH ...
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... PGCx P1A P1B P2 PGDx ... MSb © 2009 Microchip Technology Inc. PIC24FJ64GA1/GB0 FIGURE 5- PGCx P1A P1B PGDx MSb Since a 2-wire SPI is used, and data transmissions are half duplex, a simple protocol is used to control the direction of PGDx. When the programmer completes a command transmission, it releases the PGDx line and allows the programming executive to drive this line high ...
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... Additional information on error handling is provided in Section 5.3.1.3 “QE_Code Field” MSB LSB P21 PACKED INSTRUCTION WORD FORMAT LSW1 MSB1 LSW2 executive will “NACK” all © 2009 Microchip Technology Inc. ...
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... SCHECK COMMAND Opcode Length Field Description Opcode 0h Length 1h © 2009 Microchip Technology Inc. PIC24FJ64GA1/GB0 Time-out Description 1 ms Sanity check Read an 8-bit word from the specified Device ID register. 1 ms/row Read N 24-bit instruction words of code memory starting from the specified address. N/A This command is reserved ...
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... Least significant program memory word 1 ... MSB of program memory word N (zero padded) Note: Reading unimplemented memory will cause the programming executive to reset. Please ensure that only memory locations present on a particular device are accessed. © 2009 Microchip Technology Inc. 0 Length Addr_MSB Description ...
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... After the specified data word has been programmed to code memory, the programming executive verifies the programmed data against the data in the command. Expected Response (2 words): 1400h 0002h © 2009 Microchip Technology Inc. PIC24FJ64GA1/GB0 5.2.9 PROGP COMMAND ...
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... Expected Response (2 words for blank device): 1AF0h 0002h Expected Response (2 words for non-blank device): 1A0Fh 0002h Note: QBLANK does not check the system operation Configuration bits, since these bits are not set to ‘1’ when a Chip Erase is performed. © 2009 Microchip Technology Inc. 0 Length Description ...
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... Description 1h PASS Command successfully processed 2h FAIL Command unsuccessfully processed 3h NACK Command not known © 2009 Microchip Technology Inc. PIC24FJ64GA1/GB0 5.3.1 RESPONSE FORMAT All programming executive responses have a general 0 format consisting of a two-word header and any required data for the command Opcode ...
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... Section 5.2.2 “Packed Data Format”. When reading an odd number of program memory words (N odd), the response to the READP command 1)/ words. When reading an even number of program memory words (N even), the response to the READP command N words. © 2009 Microchip Technology Inc. described in ...
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... MOV 0000 EB0380 CLR 0000 000000 NOP © 2009 Microchip Technology Inc. PIC24FJ64GA1/GB0 Programming Executive”), it must be programmed into executive memory using ICSP, as described in Section 3.0 “Device Programming – ICSP”. Storing the programming executive to executive memory is similar to normal programming of code memory ...
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... GOTO 0000 000000 NOP Step 14: Repeat Steps 8 through 13 until all 16 rows of executive memory have been programmed. DS39934B-page 42 Description #<LSW0>, W0 #<MSB1:MSB0>, W1 #<LSW1>, W2 #<LSW2>, W3 #<MSB3:MSB2>, W4 #<LSW3> [W6++], [W7] [W6++], [W7++] [W6++], [W7] [W6++], [W7++] NVMCON, #15 0x200 NVMCON, W2 W2, VISI 0x200 © 2009 Microchip Technology Inc. ...
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... GOTO 0000 000000 NOP Step 6: Repeat Steps 4 and 5 until all desired executive memory is read. © 2009 Microchip Technology Inc. PIC24FJ64GA1/GB0 Reading the contents of executive memory can be performed using the same technique described in has been Section 3.8 “Reading Code Memory”. A procedure for reading executive memory is shown in Table 5-6 ...
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... DEV<7:0> DEVID REV<3:0> DEVREV DS39934B-page 44 TABLE 6-1: Device PIC24FJ32GA102 PIC24FJ64GA102 manufacturing PIC24FJ32GA104 PIC24FJ64GA104 PIC24FJ32GB002 PIC24FJ64GB002 PIC24FJ32GB004 PIC24FJ64GB004 Bit FAMID<7:0> — Description Encodes the family ID of the device Encodes the individual ID of the device Encodes the sequential (numerical) revision identifier of the device ...
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... Disabled Enabled PIC24FJ32GB004 Disabled Enabled PIC24FJ64GB002 Disabled Enabled PIC24FJ64GB004 Disabled Enabled Legend: Item Description SUM[a:b] = Byte sum of locations inclusive (all 3 bytes of code memory) CFGB = Configuration Block (masked) byte sum of (CW1 & 0x7FFF + CW2 & 0xFFFF + CW3 & 0xFFFF + CW4 & 0xFFFF) Note: CW1 address is last location of implemented program memory ...
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... See Section 2.1 DDCORE CAP pins during programming. AV and Units Conditions (1,2) V Normal programming (1,2) V Normal programming μ meet AC specifications μF Required for controller core μs μ μ µs ns should always be within ±0. © 2009 Microchip Technology Inc. ...
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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2009 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...