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MB95F116JSPMC-GE1
MB95F116JSPMC-GE1 | |
|---|---|
| Manufacturer Part Number | MB95F116JSPMC-GE1 |
| Description | 8BIT MCU, 32K FLASH, 1K RAM, LQFP52 |
| Manufacturer | Fujitsu |
| MB95F116JSPMC-GE1 datasheets |
|
Availability: By request
International delivery:
Warranty: 60 days
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- We provide standard 60-days warranty for all parts. If warranty differs we always mention it beforehand. In case of return we cover shipping costs.
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Specifications of MB95F116JSPMC-GE1 | |||
|---|---|---|---|
| Controller Family/series | F2MC-8FX | No. Of I/o's | 39 |
| Ram Memory Size | 1KB | Cpu Speed | 16.25MHz |
| No. Of Timers | 7 | No. Of Pwm | RoHS Compliant |
| Core Size | 8bit | Program Memory Size | 32KB |
| Oscillator Type | External Only | ||
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PrevNext
The RP indicates the address of the register bank currently being used. The relationship between the content
of RP and the real address conforms to the conversion rule illustrated below:
• Rule for Conversion of Actual Addresses in the General-purpose Register Area
"0"
"0"
Generated address
A15 A14 A13 A12 A11 A10
The DP specifies the area for mapping instructions (16 different instructions such as MOV A, dir) using direct
addresses to 0080
to 00FF
.
H
H
Direct bank pointer (DP2 to DP0)
XXX
(no effect to mapping)
B
000
(initial value)
B
001
B
010
B
011
B
100
B
101
B
110
B
111
B
The CCR consists of the bits indicating arithmetic operation results or transfer data contents and the bits that
control CPU operations at interrupt.
H flag
: Set to “1” when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation.
Cleared to “0” otherwise. This flag is for decimal adjustment instructions.
I flag
: Interrupt is enabled when this flag is set to “1”. Interrupt is disabled when this flag is set to “0”.
The flag is set to “0” when reset.
IL1, IL0 : Indicates the level of the interrupt currently enabled. Processes an interrupt only if its request level
is higher than the value indicated by these bits.
IL1
IL0
0
0
0
1
1
0
1
1
N flag
: Set to “1” if the MSB is set to “1” as the result of an arithmetic operation. Cleared to “0” when the
bit is set to “0”.
Z flag
: Set to “1” when an arithmetic operation results in “0”. Cleared to “0” otherwise.
V flag
: Set to “1” if the complement on 2 overflows as a result of an arithmetic operation. Cleared to “0”
otherwise.
C flag
: Set to “1” when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared
to “0” otherwise. Set to the shift-out value in the case of a shift instruction.
DS07-12611-6E
MB95110M Series
RP upper
"0"
"0"
"0"
"0"
"0"
"1"
R4
R3
A9
A8
A7
A6
Specified address area
0000
to 007F
H
H
0080
to 00FF
H
H
Interrupt level
0
1
2
3
OP code lower
R2
R1
R0
b2
b1
b0
A5
A4
A3
A2
A1
A0
Mapping area
0000
to 007F
(without mapping)
H
H
0080
to 00FF
(without mapping)
H
H
0100
to 017F
H
H
0180
to 01FF
H
H
0200
to 027F
H
H
0280
to 02FF
H
H
0300
to 037F
H
H
0380
to 03FF
H
H
0400
to 047F
H
H
Priority
High
Low ( no interruption)
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