ST62T62CB6 STMicroelectronics, ST62T62CB6 Datasheet - Page 27

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ST62T62CB6

Manufacturer Part Number
ST62T62CB6
Description
8BIT MCU OTP 2K+EEPROM, 62T62, DIP
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST62T62CB6

Controller Family/series
ST6
No. Of I/o's
9
Eeprom Memory Size
64Byte
Ram Memory Size
128Byte
Cpu Speed
8MHz
No. Of
RoHS Compliant
Core Size
8bit
Program Memory Size
1836B
Oscillator Type
External Only
Processor Series
ST62T6x
Core
ST6
Data Bus Width
8 bit
Program Memory Type
EPROM
Data Ram Size
128 B
Interface Type
SPI, UART
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
9
Number Of Timers
2
Operating Supply Voltage
3 V to 6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Package / Case
PDIP-16
Development Tools By Supplier
ST62GP-EMU2, ST62E2XC-EPB/110, ST62E6XC-EPB/US, STREALIZER-II
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / Rohs Status
 Details

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Part Number:
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0
DIGITAL WATCHDOG (Cont’d)
The Watchdog is associated with a Data space
register (Digital WatchDog Register, DWDR, loca-
tion 0D8h) which is described in greater detail in
Section 3.3.1 Digital Watchdog Register
This register is set to 0FEh on Reset: bit C is
cleared to “0”, which disables the Watchdog; the
timer downcounter bits, T0 to T5, and the SR bit
are all set to “1”, thus selecting the longest Watch-
dog timer period. This time period can be set to the
user’s requirements by setting the appropriate val-
ue for bits T0 to T5 in the DWDR register. The SR
bit must be set to “1”, since it is this bit which gen-
erates the Reset signal when it changes to “0”;
clearing this bit would generate an immediate Re-
set.
It should be noted that the order of the bits in the
DWDR register is inverted with respect to the as-
sociated bits in the down counter: bit 7 of the
DWDR register corresponds, in fact, to T0 and bit
2 to T5. The user should bear in mind the fact that
these bits are inverted and shifted with respect to
the physical counter bits when writing to this regis-
ter. The relationship between the DWDR register
bits and the physical implementation of the Watch-
dog timer downcounter is illustrated in
Only the 6 most significant bits may be used to de-
fine the time period, since it is bit 6 which triggers
the Reset when it changes to “0”. This offers the
user a choice of 64 timed periods ranging from
3,072 to 196,608 clock cycles (with an oscillator
frequency of 8MHz, this is equivalent to timer peri-
ods ranging from 384 µs to 24.576ms).
Figure
(DWDR).
17..
Figure 17. Watchdog Counter Control
D0
D1
D2
D3
D4
D5
D6
D7
ST62T52C ST62T62C/E62C
2
8
SR
T5
T4
T3
T2
T1
T0
C
OSC 12
RESET
VR02068A
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