ST62T62CB6 STMicroelectronics, ST62T62CB6 Datasheet - Page 9

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ST62T62CB6

Manufacturer Part Number
ST62T62CB6
Description
8BIT MCU OTP 2K+EEPROM, 62T62, DIP
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST62T62CB6

Controller Family/series
ST6
No. Of I/o's
9
Eeprom Memory Size
64Byte
Ram Memory Size
128Byte
Cpu Speed
8MHz
No. Of
RoHS Compliant
Core Size
8bit
Program Memory Size
1836B
Oscillator Type
External Only
Processor Series
ST62T6x
Core
ST6
Data Bus Width
8 bit
Program Memory Type
EPROM
Data Ram Size
128 B
Interface Type
SPI, UART
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
9
Number Of Timers
2
Operating Supply Voltage
3 V to 6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Package / Case
PDIP-16
Development Tools By Supplier
ST62GP-EMU2, ST62E2XC-EPB/110, ST62E6XC-EPB/US, STREALIZER-II
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / Rohs Status
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0
MEMORY MAP (Cont’d)
1.3.3 Data Space
Data Space accommodates all the data necessary
for processing the user program. This space com-
prises the RAM resource, the processor core and
peripheral registers, as well as read-only data
such
OTP/EPROM.
1.3.3.1 Data ROM
All read-only data is physically stored in program
memory, which also accommodates the Program
Space. The program memory consequently con-
tains the program code to be executed, as well as
the constants and look-up tables required by the
application.
The Data Space locations in which the different
constants and look-up tables are addressed by the
processor core may be thought of as a 64-byte
window through which it is possible to access the
read-only data stored in OTP/EPROM.
1.3.3.2 Data RAM/EEPROM
In ST62T52C, T62C and ST62E62C devices, the
data space includes 60 bytes of RAM, the accu-
mulator (A), the indirect registers (X), (Y), the short
direct registers (V), (W), the I/O port registers, the
peripheral data and control registers, the interrupt
option register and the Data ROM Window register
(DRW register).
Additional RAM and EEPROM pages can also be
addressed using banks of 64 bytes located be-
tween addresses 00h and 3Fh.
1.3.4 Stack Space
Stack space consists of six 12-bit registers which
are used to stack subroutine and interrupt return
addresses, as well as the current program counter
contents.
Table 1. Additional RAM / EEPROM Banks
ST62T52C
ST62T62C
as
Device
constants
1 x 64 bytes
1 x 64 bytes
and
RAM
look-up
1 x 64 bytes
EEPROM
tables
-
in
Table 2. ST62T52C, T62C and ST62E62C Data
* WRITE ONLY REGISTER
AR TIMER STATUS/CONTROL REGISTER1
AR TIMER STATUS/CONTROL REGISTER2
AR TIMER RELOAD/CAPTURE REGISTER
AR TIMER MODE CONTROL REGISTER
TIMER STATUS CONTROL REGISTER
AR TIMER COMPARE REGISTER
DATA ROM WINDOW REGISTER
INTERRUPT OPTION REGISTER
DATA RAM/EEPROM REGISTER
PORT C DIRECTION REGISTER
PORT A DIRECTION REGISTER
PORT B DIRECTION REGISTER
TIMER PRESCALER REGISTER
EEPROM CONTROL REGISTER
TIMER COUNTER REGISTER
PORT C OPTION REGISTER
PORT A OPTION REGISTER
PORT B OPTION REGISTER
AR TIMER LOAD REGISTER
DATA ROM WINDOW AREA
PORT C DATA REGISTER
A/D CONTROL REGISTER
PORT A DATA REGISTER
PORT B DATA REGISTER
WATCHDOG REGISTER
Memory Space
RAM / EEPROM banks
DATA RAM 60 BYTES
A/D DATA REGISTER
ACCUMULATOR
W REGISTER
X REGISTER
Y REGISTER
V REGISTER
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
ST62T52C ST62T62C/E62C
0C8h*
0C9h*
0E8h*
0CCh
0CDh
0DCh
0DDh
0CAh
0CBh
0CEh
0CFh
0DAh
0DBh
0DEh
0EAh
0EBh
03Fh
07Fh
0BFh
0C0h
0C1h
0C2h
0C3h
0C4h
0C5h
0C6h
0C7h
0D0h
0D1h
0D2h
0D3h
0D4h
0D5h
0D6h
0D7h
0D8h
0D9h
0E7h
0E9h
0FEh
0FFh
000h
040h
080h
081h
082h
083h
084h
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