UPD78F0413GA-GAM-AX NEC, UPD78F0413GA-GAM-AX Datasheet
UPD78F0413GA-GAM-AX
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UPD78F0413GA-GAM-AX Summary of contents
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... Do not use this product for mass production because its reliability cannot be guaranteed after the on-chip debug function has been used, due to issues with respect to the number of times the flash memory can be rewritten. NEC Electronics does not accept complaints concerning this product. ...
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User’s Manual U18698EJ1V0UD ...
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... IH 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction input pin is unconnected possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry ...
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... NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others ...
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Readers This manual is intended for user engineers who wish to understand the functions of the 78K0/LC3 and design and develop application systems and programs for these devices. The target products are as follows. 78K0/LC3: Purpose This manual is intended ...
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... NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Note See the “Semiconductor Device Mount Manual” website (http://www.necel.com/pkg/en/mount/index.html). Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document when designing ...
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... V .................................................................................................................................................36 DD 2.2.17 V .................................................................................................................................................36 SS 2.2.18 FLMD0 ...........................................................................................................................................36 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins........................................... 37 CHAPTER 3 CPU ARCHITECTURE...................................................................................................... 41 3.1 Memory Space .............................................................................................................................. 41 3.1.1 Internal program memory space ......................................................................................................47 3.1.2 Internal data memory space ............................................................................................................49 3.1.3 Special function register (SFR) area ................................................................................................49 3.1.4 Data memory addressing.................................................................................................................50 3 ...
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Relative addressing......................................................................................................................... 64 3.3.2 Immediate addressing..................................................................................................................... 65 3.3.3 Table indirect addressing ................................................................................................................ 66 3.3.4 Register addressing ........................................................................................................................ 66 3.4 Operand Address Addressing .................................................................................................... 67 3.4.1 Implied addressing .......................................................................................................................... 67 3.4.2 Register addressing ........................................................................................................................ 68 3.4.3 Direct addressing ............................................................................................................................ 69 ...
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Example of controlling high-speed system clock ...........................................................................127 5.6.2 Example of controlling internal high-speed oscillation clock ..........................................................129 5.6.3 Example of controlling subsystem clock ........................................................................................131 5.6.4 Example of controlling internal low-speed oscillation clock............................................................133 5.6.5 Clocks supplied to CPU and peripheral hardware ...
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Carrier generator operation (8-bit timer H1 only)............................................................................255 CHAPTER 9 REAL-TIME COUNTER................................................................................................... 262 9.1 Functions of Real-Time Counter............................................................................................... 262 9.2 Configuration of Real-Time Counter ........................................................................................ 262 9.3 Registers Controlling Real-Time Counter................................................................................ 264 9.4 Real-Time Counter Operation ................................................................................................... 276 9.4.1 Starting ...
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Calculation of baud rate ...............................................................................................................331 CHAPTER 14 SERIAL INTERFACE UART6 ...................................................................................... 335 14.1 Functions of Serial Interface UART6...................................................................................... 335 14.2 Configuration of Serial Interface UART6 ............................................................................... 339 14.3 Registers Controlling Serial Interface UART6....................................................................... 342 14.4 Operation of Serial Interface ...
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... Internal Memory Size Switching Register.............................................................................. 508 24.2 Writing with Flash memory programmer ............................................................................... 509 24.3 Programming Environment ..................................................................................................... 511 24.4 Communication Mode .............................................................................................................. 511 24.5 Connection of Pins on Board.................................................................................................. 513 24.5.1 FLMD0 pin ...................................................................................................................................513 24.5.2 Serial interface pins......................................................................................................................513 24.5.3 RESET pin ...................................................................................................................................515 24.5.4 Port pins.......................................................................................................................................515 12 User’ ...
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... Security Settings...................................................................................................................... 520 24.8 Flash Memory Programming by Self-Programming (Under Development) ....................... 522 24.8.1 Boot swap function.......................................................................................................................524 CHAPTER 25 ON-CHIP DEBUG FUNCTION ..................................................................................... 526 25.1 Connecting QB-78K0MINI to 78K0/LC3 .................................................................................. 526 25.2 On-Chip Debug Security ID ..................................................................................................... 527 CHAPTER 26 INSTRUCTION SET ...................................................................................................... 528 26.1 Conventions Used in Operation List...................................................................................... 528 26 ...
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... Real-time counter (RTC): 1 channel Watchdog timer: Serial interface: 2 channels UART (LIN (Local Interconnect Network)-bus supported): 1 channel UART: 10-bit successive approximation type A/D converter: 6 channels ( PD78F041x only) Manchester code generator Power supply voltage 1.8 to 5.5 V ...
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Applications Digital cameras, AV equipments, household electrical appliances, utility meters, health care equipments, and measurement equipment, etc. 1.3 Ordering Information Flash memory version (Lead-free products) Part Number PD78F0400GA-GAM-AX 48-pin plastic LQFP (fine pitch) (7 PD78F0401GA-GAM-AX 48-pin plastic LQFP (fine ...
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... FLMD0 OCD0B/EXCLK/X2/P122 OCD0A/X1/P121 REGC Cautions 1. Connect the REGC pin Only the bottom side pins (pin numbers 23 and 24) correspond to the UART6 pins (RxD6 and TxD6) when writing by a flash memory programmer. Writing cannot be performed by the top side pins (pin numbers 48 and 47). ...
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... Cautions 1. Connect the AV pin Connect the REGC pin ANI0/P20 to ANI5/P25 are set in the analog input mode after release of reset. 4. Only the bottom side pins (pin numbers 23 and 24) correspond to the UART6 pins (RxD6 and TxD6) when writing by a flash memory programmer. Writing cannot be performed by the top side pins (pin numbers 48 and 47). Remark The functions within arrowheads (< ...
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Pin Identification Note ANI0 to ANI5 : Analog input Note AV : Analog reference voltage REF Note AV : Analog ground SS BUZ: Buzzer output COM0 to COM7: Common output EXCLK: External clock input (main system clock) EXLVI: External potential ...
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Microcontroller Series Lineup ROM RAM 78K0/LC3 48 Pins PD78F0413 PD78F0403 PD78F0412 PD78F0402 16 KB 768 B PD78F0411 PD78F0401 8 KB 512 B ...
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The list of functions in the 78K0/Lx3 Microcontrollers is shown below. Part Number PD78F040x Item Flash memory (KB RAM (KB) 0.5 0.75 Power supply voltage Regulator Minimum instruction execution time High-speed system clock Internal high-speed oscillation clock Subclock ...
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Part Number PD78F044x Item Flash memory (KB RAM (KB) 0.75 1 Power supply voltage Regulator Minimum instruction execution time High-speed system clock Internal high-speed oscillation clock Subclock Internal low-speed oscillation clock Total 16 bits (TM0) 8 bits (TM5) ...
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Part Number PD78F047x Item Flash memory (KB RAM (KB) 0.75 1 Power supply voltage Regulator Minimum instruction execution time High-speed system clock Internal high-speed oscillation clock Subclock Internal low-speed oscillation clock Total 16 bits (TM0) 8 bits (TM5) ...
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Block Diagram RxD6/P113, RxD6/P12 (LINSEL) TI000/P33 16-bit TIMER/ EVENT COUNTER 00 TO00/TI010/P34 TOH0/P32 8-bit TIMER H0 TOH1/P31 8-bit TIMER H1 8-bit TIMER H2 INTERNAL LOW-SPEED OSCILLATOR WATCHDOG TIMER LCD CONTROLLER 22 SEG0 to SEG21 DRIVER 8 COM0 to COM7 ...
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Outline of Functions Item Internal Flash memory 8 KB memory (self-programming Note supported) Note High-speed RAM 512 bytes LCD display RAM 22 Memory space 64 KB Main system High-speed system X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK) ...
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Item successive approximation 10-bit • PD78F040x: None type A/D converter • PD78F041x: 6 channels Serial interface • UART supporting LIN-bus • UART: 1 channel LCD controller/driver • External resistance division and internal resistance division are switchable. • Segment signal outputs: ...
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... Notes 1. In the real-time counter, the Interval timer function and calendar function can be used simultaneously. 2. TM52 and TM00 can be connected in cascade to be used as a 24-bit counter. Also, the external event input of TM52 can be input enable-controlled via TMH2. 3. TM51 and TMH1 can be used in combination as a carrier generator mode. ...
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Pin Function List There are three types of pin I/O buffer power supplies: AV power supplies and the pins is shown below. Power Supply Note AV REF V LC0 V DD Note PD78F041x only. The power supply is V ...
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Port pins Function Name I/O P100, P101 I/O Port 10. 2-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P112 I/O Port 11. 2-bit I/O ...
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Non-port pins Function Name I/O Note successive approximation type ANI0 Input 10-bit analog input. Note ANI1 Note ANI2 Note ANI3 Note ANI4 Note ANI5 Note successive approximation type AV Input 10-bit REF reference voltage input, positive power supply for ...
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... Serial data output from asynchronous serial interface TxD6 <TxD6> EXLVI Input Potential input for external low-voltage detection X1 Input Connecting resonator for main system clock X2 EXCLK Input External clock input for main system clock XT1 Input Connecting resonator for subsystem clock XT2 ...
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Description of Pin Functions 2.2.1 P12, P13 (port 1) P12 and P13 function as a 2-bit I/O port. These pins also function as pins for key interrupt and serial interface data I/O. P13 can be selected to function as ...
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P31 to P34 (port 3) P31 to P34 function as a 4-bit I/O port. These pins also function as pins for external interrupt request input, timer I/O, buzzer output, real-time counter output, and manchester code output. The following operation ...
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P40 (port 4) P40 functions as a 1-bit I/O port. These pins also function as pins for key interrupt input and power supply voltage for driving the LCD. The following operation modes can be specified in 1-bit units. (1) ...
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... P120 functions as a 1-bit I/O port. P121 to P124 function as a 4-bit input port. These pins also function as pins for external interrupt request input, potential input for external low-voltage detection, resonator for main system clock connection, resonator for subsystem clock connection, and external clock input. The following operation modes can be specified in 1-bit units. ...
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... This is the 10-bit successive approximation type A/D converter reference voltage input pin and the positive power supply pin of port 2. When the A/D converter is not used, connect this pin directly to V Note When one or more of the pins of port 2 is used as the digital port pins or for segment output, make AV the same potential as V ...
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... REGC This is the pin for connecting regulator output (2.4 V) stabilization capacitance for internal operation. Connect this pin to V via a capacitor (0. recommended). SS Caution Keep the wiring length as short as possible in the area enclosed by the broken lines in the above figures. 2.2. This is the positive power supply pin. ...
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... Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-2 shows the types of pin I/O circuits and the recommended connections of unused pins. See Figure 2-1 for the configuration of the I/O circuit of each type. Pin Name I/O Circuit Type P12/RxD0/KR3/<RxD6> ...
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... REF Note Notes 1. Use recommended connection above in I/O port mode (see Figure 5-2 Format of Clock Operation Mode Select Register (OSCCTL)) when these pins are not used. 2. PD78F041x only. 3. FLMD0 is a pin used when writing data to flash memory. When rewriting flash memory data on-board or performing on-chip debugging, connect this pin ...
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Type 2 IN Schmitt-triggered input with hysteresis characteristics Type 5-AG Pull-up enable V DD Data P-ch Output N-ch disable V SS Input enable Type 5-AH Pull-up enable V DD Data P-ch Output N-ch disable V SS Input enable CHAPTER 2 ...
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Type 17-R P-ch DSn±/REF± N- Comparator P-ch + ANI _ N-ch AV REF AV REF AV SS data P-ch output N-ch disable AV SS input enable P-ch V LC0 P-ch V LC1 N-ch P-ch SEG data N-ch P-ch ...
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Memory Space Each products in the 78K0/LC3 can access memory space. Figures 3-1 to 3-4 show the memory maps. Caution Regardless of the internal memory capacity, the initial values of the internal memory size switching register ...
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Figure 3-1. Memory Map ( PD78F0400, 78F0410 Special function registers (SFR) 256 x 8 bits General-purpose registers bits ...
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Figure 3-2. Memory Map ( PD78F0401, 78F0411 Special function registers (SFR) 256 x 8 bits General-purpose registers bits ...
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Figure 3-3. Memory Map ( PD78F0402, 78F0412 Special function registers (SFR) 256 x 8 bits General-purpose registers bits ...
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Figure 3-4. Memory Map ( PD78F0403, 78F0413 Special function registers (SFR) 256 x 8 bits General-purpose registers bits ...
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Correspondence between the address values and block numbers in the flash memory are shown below. Table 3-2. Correspondence Between Address Values and Block Numbers in Flash Memory Address Value 0000H to 03FFH 0400H to 07FFH 0800H to 0BFFH 0C00H to ...
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Internal program memory space The internal program memory space stores the program and table data. Normally addressed with the program counter (PC). 78K0/LC3 products incorporate internal ROM (flash memory), as shown below. Part Number PD78F0400, 78F0410 Flash ...
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CALLT instruction table area The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT). (3) Option byte area A 5-byte area of 0080H to 0084H and 1080H to 1084H can be ...
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Internal data memory space 78K0/LC3 products incorporate the following RAMs. (1) Internal high-speed RAM Table 3-5. Internal High-Speed RAM Capacity Part Number PD78F0400, 78F0410 PD78F0401, 78F0411 PD78F0402, 78F0412 PD78F0403, 78F0413 This area cannot be used as a program area ...
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Data memory addressing Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. Several addressing modes are provided for ...
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CHAPTER 3 CPU ARCHITECTURE Figure 3-6. Correspondence Between Data Memory and Addressing ( PD78F0401, 78F0411 Special function registers (SFR) 256 x 8 bits ...
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Figure 3-7. Correspondence Between Data Memory and Addressing ( PD78F0402, 78F0412 Special function registers (SFR) 256 x 8 bits ...
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CHAPTER 3 CPU ARCHITECTURE Figure 3-8. Correspondence Between Data Memory and Addressing ( PD78F0403, 78F0413 Special function registers (SFR) 256 x 8 bits ...
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Processor Registers The 78K0/LC3 products incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and ...
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Zero flag (Z) When the operation result is zero, this flag is set (1 reset (0) in all other cases. (c) Register bank select flags (RBS0 and RBS1) These are 2-bit flags to select one of the ...
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Figure 3-12. Data to Be Saved to Stack Memory (a) PUSH rp instruction (when SP = FEE0H (b) CALL, CALLF, CALLT instructions (when SP = FEE0H (c) Interrupt, BRK instructions (when SP = FEE0H ...
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CHAPTER 3 CPU ARCHITECTURE Figure 3-13. Data to Be Restored from Stack Memory (a) POP rp instruction (when SP = FEDEH) FEE0H FEE0H SP FEDFH FEDEH SP FEDEH (b) RET instruction (when SP = FEDEH) FEE0H FEE0H SP FEDFH FEDEH ...
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General-purpose registers General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. The general-purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers ( and H). ...
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Special function registers (SFRs) Unlike a general-purpose register, each special function register has a special function. SFRs are allocated to the FF00H to FFFFH areas in the CPU, and are allocated to the 00H to 03H areas of LCDCTL ...
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Table 3-6. Special Function Register List (1/4) Address Special Function Register (SFR) Name FF00H Receive buffer register 6 FF01H Port register 1 FF02H Port register 2 FF03H Port register 3 FF04H Port register 4 FF05H Transmit buffer register 6 FF06H ...
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Table 3-6. Special Function Register List (2/4) Address Special Function Register (SFR) Name FF3CH Pull-up resistor option register 12 FF3EH Pull-up resistor option register 14 FF3FH Pull-up resistor option register 15 FF40H Clock output selection register FF41H 8-bit timer compare ...
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Table 3-6. Special Function Register List (3/4) Address Special Function Register (SFR) Name FF66H Day count register FF67H Month count register FF68H Year count register FF69H 8-bit timer H mode register 0 FF6AH Timer clock selection register 50 FF6BH 8-bit ...
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Table 3-6. Special Function Register List (4/4) Address Special Function Register (SFR) Name FFB0H LCD mode register FFB1H LCD display mode register FFB2H LCD clock control register 0 FFB5H Port function register 2 FFB6H Port function register ALL FFBAH 16-bit ...
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Instruction Address Addressing An instruction address is determined by contents of the program counter (PC), and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another ...
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Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and ...
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Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits the immediate data of an operation code are transferred to the program counter (PC) and branched. This ...
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... ROR4/ROL4 A register for storage of digit data that undergoes digit rotation [Operand format] Because implied addressing can be automatically determined with an instruction, no particular operand format is necessary. [Description example] In the case of MULU X With an 8-bit 8-bit multiply instruction, the product of the A register and X register is stored in AX. In this example, the A and AX registers are specified by implied addressing ...
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Register addressing [Function] The general-purpose register to be specified is accessed as an operand with the register bank select flags (RBS0 to RBS1) and the register specify codes of an operation code. Register addressing is carried out when an ...
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Direct addressing [Function] The memory to be manipulated is directly addressed with immediate data in an instruction word becoming an operand address. [Operand format] [Description example] MOV A, !0FE00H; when setting !addr16 to FE00H Operation code [Illustration] 7 CHAPTER ...
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Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte space FE20H to FF1FH. Internal high-speed RAM and special ...
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Special function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the ...
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Register indirect addressing [Function] Register pair contents specified by a register pair specify code in an instruction word and by a register bank select flag (RBS0 and RBS1) serve as an operand address for addressing the memory. This addressing ...
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Based addressing [Function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and ...
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Based indexed addressing [Function] The register contents specified in an instruction word are added to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank ...
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Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call and return instructions are executed or the register is saved/reset upon generation ...
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Port Functions There are two types of pin I/O buffer power supplies: AV supplies and the pins is shown below. Power Supply Note AV REF V DD Note PD78F041x only. The power supply is V 78K0/LC3 products are provided ...
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Function Name I/O P12 I/O Port 1. 2-bit I/O port. P13 Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P20 I/O Port 2. 6-bit I/O port. P21 Input/output ...
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Port Configuration Ports include the following hardware. Item Control registers Port mode register (PM1 to PM4, PM10 to PM12, PM14, PM15) Port register (P1 to P4, P10 to P12, P14, P15) Pull-up resistor option register (PU1, PU3, PU4, PU10 ...
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Port 1 Port 2-bit I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (PM1). When the P12 and P13 ...
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WR PU PU1 PU13 Alternate function PM1 PM13 WR PORT P1 Output latch (P13) Serial interface UART0 Serial interface UART6 WR PF PF1 PF13 P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode ...
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Port 2 Port 6-bit I/O port with an output latch. Port 2 can be set to the input mode or output mode in 1-bit units using port mode register 2 (PM2). This port can also be ...
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WR PU PU2 PU20 to PU25 Note A/D converter RD WR PORT P2 Output latch (P20 to P25 PM2 PM20 to PM25 LCD controller/driver WR PF PF2 PF20 to PF25 Note PD78F041x only. P2: Port register 2 PU2: ...
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Port 3 Port 4-bit I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units using port mode register 3 (PM3). When the P31 to P34 ...
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WR PU PU3 PU32 RD WR PORT P3 Output latch (P32 PM3 PM32 Alternate function P3: Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 RD: Read signal WR : Write signal 84 ...
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Port 4 Port 1-bit I/O port with an output latch. Port 4 can be set to the input mode or output mode in 1-bit units using port mode register 4 (PM4). When the P40 pin is ...
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Port 10 Port 2-bit I/O port with an output latch. Port 10 can be set to the input mode or output mode in 1-bit units using port mode register 10 (PM10). When the P100 and P101 ...
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Port 11 Port 2-bit I/O port with an output latch. Port 11 can be set to the input mode or output mode in 1-bit units using port mode register 11 (PM11). When the P112, P113 pins ...
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WR PU PU11 PU113 Alternate function RD WR PORT P11 Output latch (P113 PM11 PM113 LCD controller/driver WR PF PFALL PF11ALL P11: Port register 11 PU11: Pull-up resistor option register 11 PM11: Port mode register 11 PFALL: Port ...
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... Figures 4-11 to 4-13 show block diagrams of port 12. Caution When using the P121 to P124 pins to connect a resonator for the main system clock (X1, X2) or subsystem clock (XT1, XT2 input an external clock for the main system clock (EXCLK), the X1 oscillation mode, XT1 oscillation mode, or external clock input mode must be set by using the clock operation mode select register (OSCCTL) (for details, see 5 ...
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WR PU PU12 PU120 Alternate function RD WR PORT P12 Output latch (P120 PM12 PM120 P12: Port register 12 PU12: Pull-up resistor option register 12 PM12: Port mode register 12 RD: Read signal WR : Write signal 90 ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-12. Block Diagram of P121 and P122 OSCSEL RD RD OSCCTL: Clock operation mode select register RD: Read signal User’s Manual U18698EJ1V0UD OSCCTL OSCCTL EXCLK, OSCSEL P122/X2/EXCLK/OCD0B P121/X1/OCD0A 91 ...
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Figure 4-13. Block Diagram of P123 and P124 RD RD OSCCTL: Clock operation mode select register RD: Read signal 92 CHAPTER 4 PORT FUNCTIONS OSCCTL OSCSELS OSCCTL OSCSELS User’s Manual U18698EJ1V0UD P124/XT2 P123/XT1 ...
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Port 14 Port 4-bit I/O port with an output latch. Port 14 can be set to the input mode or output mode in 1-bit units using port mode register 14 (PM14). When the P140 to P143 ...
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Port 15 Port 4-bit I/O port with an output latch. Port 15 can be set to the input mode or output mode in 1-bit units using port mode register 15 (PM15). When the P150 to P153 ...
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Registers Controlling Port Function Port functions are controlled by the following seven types of registers. Port mode registers (PM1 to PM4, PM10 to PM12, PM14, PM15) Port registers (P1 to P4, P10 to P12, P14, P15) Pull-up resistor option ...
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Figure 4-16. Format of Port Mode Register Symbol PM1 PM2 PM25 PM3 PM4 PM10 PM11 PM12 PM14 ...
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Port registers (P1 to P4, P10 to P12, P14, P15) These registers write the data that is output from the chip when data is output from a port. If the data is read in the input mode, the pin ...
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... PU1, PU3, PU4, PU10 to PU12, PU14, and PU15. On-chip pull-up resistors cannot be connected to bits set to output mode and bits used as alternate-function output pins, regardless of the settings of PU1, PU3, PU4, PU10 to PU12, PU14, and PU15 ...
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Port function register 1 (PF1) This register sets the pin functions of P13/TxD0/KR4/<TxD6> pins. PF1 is set using a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PF1 to 00H. Remark The functions within arrowheads (< >) ...
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Port function register ALL (PFALL) This register sets whether to use pins P10, P11, P14, and P15 as port pins (other than segment output pins) or segment output pins. PFALL is set using a 1-bit or 8-bit memory manipulation ...
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A/D port configuration register 0 (ADPC0) ( PD78F041x only) This register switches the P20/ANI0 to P25/ANI5 pins to analog input of A/D converter or digital I/O of port. ADPC0 can be set by a 1-bit or 8-bit memory manipulation ...
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Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. Caution In the case of 1-bit memory manipulation instruction, although a single bit is manipulated, the port is accessed as ...
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Settings of PFALL, PF2, PF1, ISC, Port Mode Register, and Output Latch When Using Alternate Function To use the alternate function of a port pin, set the port mode register and output latch as shown in Table 4-5. Table ...
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Table 4-5. Settings of PFALL, PF2, PF1, ISC, Port Mode Register, and Output Latch When Using Pin Name Alternate Function Function I/O Name P113 SEG7 Output RxD6 Input P120 EXLVI Input INTP0 Input Note 3 P121 X1 OCD0A Note 3 ...
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... PD78F041x only. 3. When using the P121 to P124 pins to connect a resonator for the main system clock (X1, X2) or subsystem clock (XT1, XT2 input an external clock for the main system clock (EXCLK), the X1 oscillation mode, XT1 oscillation mode, or external clock input mode must be set by using the clock operation mode select register (OSCCTL) (for details, see 5 ...
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... External main system clock frequency EXCLK XT1 clock oscillation frequency XT 106 CHAPTER 5 CLOCK GENERATOR = MHz by connecting a resonator to X1 and X2 MHz (TYP.). After a reset release, the CPU always starts MHz) can also be supplied from the OCD0B/EXCLK/X2/P122 EXCLK = 32.768 kHz by connecting a 32.768 kHz resonator across XT1 XT ...
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Internal low-speed oscillation clock (clock for watchdog timer) Internal low-speed oscillator This circuit oscillates a clock of f clock always starts operating. Oscillation can be stopped by using the internal oscillation mode register (RCM) when “internal low-speed oscillator can ...
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Clock operation mode Main OSC control register select register (OSCCTL) (MOC) EXCLK OSCSEL MSTOP High-speed system clock oscillator f XH X1/P121 Crystal/ceramic f X oscillation X2/EXCLK/ External input P122 f Internal high- EXCLK f clock RH speed oscillator (8 MHz ...
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Remarks clock oscillation frequency Internal high-speed oscillation clock frequency External main system clock frequency EXCLK High-speed system clock frequency Main system ...
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... CHAPTER 5 CLOCK GENERATOR R/W 5 <4> OSCSELS 0 High-speed system clock P121/X1 pin pin operation mode Input port mode Input port X1 oscillation mode Crystal/ceramic resonator connection Input port mode Input port External clock input Input port mode User’s Manual U18698EJ1V0UD P122/X2/EXCLK pin ...
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Processor clock control register (PCC) This register is used to select the CPU clock, the division ratio, and operation mode for subsystem clock. PCC is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PCC ...
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... Subsystem Clock Pin P123/XT1 Pin Operation Mode Input port mode Input port XT1 oscillation mode Crystal resonator connection User’s Manual U18698EJ1V0UD CPU Subsystem Clock At 32.768 kHz Operation 122.1 s P124/XT2 Pin ...
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Internal oscillation mode register (RCM) This register sets the operation mode of internal oscillator. RCM can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 80H Figure 5-4. Format of Internal ...
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Main OSC control register (MOC) This register selects the operation mode of the high-speed system clock. This register is used to stop the X1 oscillator or to disable an external clock input from the EXCLK pin when the CPU ...
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Main clock mode register (MCM) This register selects the main system clock supplied to CPU clock and clock supplied to peripheral hardware clock. MCM can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears ...
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Oscillation stabilization time counter status register (OSTC) This is the register that indicates the count status of the X1 clock oscillation stabilization time counter. When X1 clock oscillation starts with the internal high-speed oscillation clock or subsystem clock used ...
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Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released. When the X1 clock is selected as the CPU clock, the operation waits for ...
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Internal high-speed oscillation trimming register (HIOTRM) This register corrects the accuracy of the internal high-speed oscillator. The accuracy can be corrected by self- measuring the frequency of the internal high-speed oscillator, using a subsystem clock using a crystal resonator ...
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Figure 5-9. Format of Internal High-speed Oscillation Trimming Register (HIOTRM) Address: FF30H After reset: 10H R/W Symbol 7 6 HIOTRM 0 0 TTRM4 TTRM3 ...
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... System Clock Oscillator 5.4.1 X1 oscillator The X1 oscillator oscillates with a crystal resonator or ceramic resonator ( MHz) connected to the X1 and X2 pins. An external clock can also be input. In this case, input the clock signal to the EXCLK pin. Figure 5-10 shows an example of the external circuit of the X1 oscillator. ...
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... Figure 5-12 shows examples of incorrect resonator connection. Figure 5-12. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert resistors in series on the XT2 side. CHAPTER 5 CLOCK GENERATOR (b) Crossed signal line ...
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... Figure 5-12. Examples of Incorrect Resonator Connection (2/2) (c) Wiring near high alternating current (e) Signals are fetched Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert resistors in series on the XT2 side. Caution 2. When X2 and XT1 are wired in parallel, the crosstalk noise of X2 may increase with XT1, resulting in malfunctioning ...
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... When subsystem clock is not used not necessary to use the subsystem clock for low power consumption operations not using the subsystem clock as an I/O port, set the XT1 and XT2 pins to Input port mode (OSCSELS = 0) and independently connect via a resistor Remark OSCSELS: Bit 4 of clock operation mode select register (OSCCTL) 5 ...
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... When the X1 clock is set as the CPU clock by the default setting, the device cannot operate if the X1 clock is damaged or badly connected and therefore does not operate after reset is released. However, the start clock of the CPU is the internal high-speed oscillation clock, so the device can be started by the internal high-speed oscillation clock after a reset release ...
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... Figure 5-14). By doing so, the CPU operates with the same timing as <2> and thereafter in Figure 5-13 after reset release by the RESET pin not necessary to wait for the oscillation stabilization time when an external clock input from the EXCLK pin is used. CHAPTER 5 CLOCK GENERATOR ...
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... V (TYP.). If the supply voltage rises from 1.59 V (TYP.) to 2.7 V (TYP.) within 1.93 ms, the power supply oscillation stabilization time 5. automatically generated before reset processing not necessary to wait for the oscillation stabilization time when an external clock input from the EXCLK pin is used. 126 CHAPTER 5 CLOCK GENERATOR 2 ...
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... Example of controlling high-speed system clock The following two types of high-speed system clocks are available. X1 clock: Crystal/ceramic resonator is connected across the X1 and X2 pins. External main system clock: External clock is input to the EXCLK pin. When the high-speed system clock is not used, the OCD0A/X1/P121 and OCD0B/X2/EXCLK/P122 pins can be used as I/O port pins ...
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... Example of setting procedure when oscillating the X1 clock and (2) Example of setting procedure when using the external main system clock.) Note The setting of <1> is not necessary when high-speed system clock is already operating. <2> Setting the high-speed system clock as the main system clock (MCM register) When XSEL and MCM0 are set to 1, the high-speed system clock is supplied as the main system clock and peripheral hardware clock ...
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Example of setting procedure when stopping the high-speed system clock The high-speed system clock can be stopped in the following two ways. Executing the STOP instruction to set the STOP mode Setting MSTOP to 1 and stopping the X1 ...
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... Notes 1. After a reset release, the internal high-speed oscillator automatically starts oscillating and the internal high-speed oscillation clock is selected as the CPU clock. 2. This wait time is not necessary if high accuracy is not necessary for the CPU clock and peripheral hardware clock. (2) Example of setting procedure when using internal high-speed oscillation clock as CPU clock, and internal high-speed oscillation clock or high-speed system clock as peripheral hardware clock < ...
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... The following two types of subsystem clocks are available. XT1 clock: Crystal/ceramic resonator is connected across the XT1 and XT2 pins. When the subsystem clock is not used, the XT1/P123 and XT2/P124 pins can be used as Input port pins. Caution The XT1/P123 and XT2/P124 pins are in the Input port mode after a reset release. ...
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... Setting subsystem clock oscillation (See 5.6.3 (1) Example of setting procedure when oscillating the XT1 clock) Note The setting of <1> is not necessary when while the subsystem clock is operating. <2> Switching the CPU clock (PCC register) When CSS is set to 1, the subsystem clock is supplied to the CPU. ...
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Example of controlling internal low-speed oscillation clock The internal low-speed oscillation clock cannot be used as the CPU clock. Only the following peripheral hardware can operate with this clock. Watchdog timer 7 8-bit timer H1 ( ...
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CPU clock status transition diagram Figure 5-15 shows the CPU clock status transition diagram of this product. Figure 5-15. CPU Clock Status Transition Diagram (When 1.59 V POC Mode Is Set (Option Byte: POCMODE = 0)) Internal low-speed oscillation: ...
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... Bit 4 of the processor clock control register (PCC) CHAPTER 5 CLOCK GENERATOR SFR Register Setting SFR registers do not have to be set (default status after reset release). EXCLK OSCSEL OSCSELS Waiting for Oscillation Stabilization 1 Necessary User’s Manual U18698EJ1V0UD MSTOP OSTC XSEL MCM0 Register 0 Must checked 0 1 ...
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... Note The value of this flag can be changed only once after a reset release. This setting is not necessary if it has already been set. Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see CHAPTER 27 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)) ...
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... Remarks 1. (A) to (I) in Table 5-5 correspond to (A) to (I) in Figure 5-15. 2. MCM0: OSCSELS: RSTS, RSTOP: CSS: CHAPTER 5 CLOCK GENERATOR RSTOP 0 Confirm this flag is 1. Unnecessary if the CPU is operating with the internal high-speed oscillation clock OSCSELS Waiting for Oscillation 1 Unnecessary if the CPU is operating with the subsystem clock RSTOP RSTS ...
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... Note The value of this flag can be changed only once after a reset release. This setting is not necessary if it has already been set. Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see CHAPTER 27 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)) ...
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Condition before changing CPU clock and processing after changing CPU clock Condition before changing the CPU clock and processing after changing the CPU clock are shown below. CPU Clock Before Change After Change Internal high- X1 clock Stabilization of ...
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Time required for switchover of CPU clock and main system clock By setting bits (PCC0 to PCC2) and bit 4 (CSS) of the processor clock control register (PCC), the CPU clock can be switched (between the ...
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Table 5-8. Maximum Time Required for Main System Clock Switchover Set Value Before Switchover MCM0 0 1 Caution When switching the internal high-speed oscillation clock to the high-speed system clock, bit 2 (XSEL) of MCM must be set to 1 ...
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Peripheral hardware and source clocks The following lists peripheral hardware and source clocks incorporated in the 78K0/LC3. Table 5-10. Peripheral Hardware and Source Clocks Source Clock Peripheral Hardware Clock (f PRS Peripheral Hardware 16-bit timer event counter ...
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... 16-bit timer/event counter 00 can measure the pulse width of an externally input signal. (7) 24-bit external event counter 16-bit timer/event counter 00 can be operated to function as an external 24-bit event counter, by connecting 16- bit timer/event counter 00 and 8-bit timer/event counter 52 in cascade, and using the external event counter function of 8-bit timer/event counter 52 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.2 Configuration of 16-Bit Timer/Event Counter 00 16-bit timer/event counter 00 includes the following hardware. Table 6-1. Configuration of 16-Bit Timer/Event Counter 00 Item Time/counter Register Timer input Timer output Control registers Remark When ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 Cautions 2. If clearing of bits 3 and 2 (TMC003 and TMC002) of 16-bit timer mode control register 00 (TMC00 and input of the capture trigger conflict, then the captured data is ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-3. Format of 16-Bit Timer Capture/Compare Register 000 (CR000) Address: FF12H, FF13H CR000 (i) When CR000 is used as a compare register The value set in CR000 is constantly compared ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 (iii) Setting range when CR000 or CR010 is used as a compare register When CR000 or CR010 is used as a compare register, set it as shown below. Operation Operation as interval timer Operation ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Table 6-2. Capture Operation of CR000 and CR010 External Input Signal TI000 Pin Input Capture Operation Capture operation of CRC001 = 1 CR000 TI000 pin input (reverse phase) Interrupt signal Note Capture operation of ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 6.3 Registers Controlling 16-Bit Timer/Event Counter 00 Registers used to control 16-bit timer/event counter 00 are shown below. 16-bit timer mode control register 00 (TMC00) Capture/compare control register 00 (CRC00) 16-bit timer output control ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-5. Format of 16-Bit Timer Mode Control Register 00 (TMC00) Address: FFBAH After reset: 00H Symbol 7 6 TMC00 0 0 TMC003 TMC002 TMC001 0 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 (2) Capture/compare control register 00 (CRC00) CRC00 is the register that controls the operation of CR000 and CR010. Changing the value of CRC00 is prohibited during operation (when TMC003 and TMC002 = other than ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-7. Example of CR010 Capture Operation (When Rising Edge Is Specified) Count clock TM00 TI000 Rising edge detection CR010 INTTM010 (3) 16-bit timer output control register 00 (TOC00) TOC00 is an 8-bit register ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 Figure 6-8. Format of 16-Bit Timer Output Control Register 00 (TOC00) Address: FFBDH After reset: 00H R/W Symbol 7 <6> TOC00 0 OSPT00 OSPT00 0 1 One-shot pulse output The value of this bit ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (4) Prescaler mode register 00 (PRM00) PRM00 is the register that sets the TM00 count clock and TI000 and TI010 pin input valid edges. Rewriting PRM00 is prohibited during operation (when TMC003 and TMC002 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 Figure 6-9. Format of Prescaler Mode Register 00 (PRM00) Address: FFBBH After reset: 00H Symbol 7 6 PRM00 ES101 ES100 ES101 ES100 ES001 ES000 0 0 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (5) Input switch control register (ISC) The input source to TI000 becomes the input signal from the P33/TI000 pin, by setting ISC1 to 0. ISC can be set by a 1-bit or 8-bit memory ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 (6) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P34/TI52/TI010/TO00/RTC1HZ/INTP1 pin for timer output, set PM34 and the output latches of P34 to 0. When ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4 Operation of 16-Bit Timer/Event Counter 00 6.4.1 Interval timer operation If bits 3 and 2 (TMC003 and TMC002) of the 16-bit timer mode control register (TMC00) are set to 11 (clear & start ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 Figure 6-14. Example of Register Settings for Interval Timer Operation (a) 16-bit timer mode control register 00 (TMC00 (b) Capture/compare control register 00 (CRC00 (c) 16-bit ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-15. Example of Software Processing for Interval Timer Function TM00 register 0000H Operable bits 00 (TMC003, TMC002) CR000 register INTTM000 signal <1> <1> Count operation start flow START Register initial setting PRM00 register, ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 6.4.2 Square wave output operation When 16-bit timer/event counter 00 operates as an interval timer (see 6.4.1), a square wave can be output from the TO00 pin by setting the 16-bit timer output control ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-18. Example of Register Settings for Square Wave Output Operation (a) 16-bit timer mode control register 00 (TMC00 (b) Capture/compare control register 00 (CRC00 (c) ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 Figure 6-19. Example of Software Processing for Square Wave Output Function TM00 register 0000H Operable bits 00 (TMC003, TMC002) CR000 register TO00 output INTTM000 signal TO00 output control bit (TOC001, TOE00) <1> <1> Count ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.3 External event counter operation When bits 1 and 0 (PRM001 and PRM000) of the prescaler mode register 00 (PRM00) are set to 11 (for counting up with the valid edge of the TI000 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 Figure 6-21. Example of Register Settings in External Event Counter Mode (1/2) (a) 16-bit timer mode control register 00 (TMC00 (b) Capture/compare control register 00 (CRC00 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-21. Example of Register Settings in External Event Counter Mode (2/2) (e) 16-bit timer counter 00 (TM00) By reading TM00, the count value can be read. (f) 16-bit capture/compare register 000 (CR000) If ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 Figure 6-22. Example of Software Processing in External Event Counter Mode TM00 register 0000H Operable bits 00 (TMC003, TMC002) Compare register (CR000) TO00 output Compare match interrupt (INTTM000) TO00 output control bits (TOC004, TOC001, ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.4 Operation in clear & start mode entered by TI000 pin valid edge input When bits 3 and 2 (TMC003 and TMC002) of 16-bit timer mode control register 00 (TMC00) are set to 10 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 Figure 6-24. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input (CR000: Compare Register, CR010: Compare Register) (a) TOC00 = 13H, PRM00 = 10H, CRC00, = 00H, TMC00 = ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (2) Operation in clear & start mode entered by TI000 pin valid edge input (CR000: compare register, CR010: capture register) Figure 6-25. Block Diagram of Clear & Start Mode Entered by TI000 Pin Valid ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 Figure 6-26. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input (CR000: Compare Register, CR010: Capture Register) (2/2) (b) TOC00 = 13H, PRM00 = 10H, CRC00, = 04H, TMC00 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (3) Operation in clear & start mode by entered TI000 pin valid edge input (CR000: capture register, CR010: compare register) Figure 6-27. Block Diagram of Clear & Start Mode Entered by TI000 Pin Valid ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 Figure 6-28. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input (CR000: Capture Register, CR010: Compare Register) (1/2) (a) TOC00 = 13H, PRM00 = 10H, CRC00, = 03H, TMC00 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-28. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input (CR000: Capture Register, CR010: Compare Register) (2/2) (b) TOC00 = 13H, PRM00 = 10H, CRC00, = 03H, TMC00 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 (4) Operation in clear & start mode entered by TI000 pin valid edge input (CR000: capture register, CR010: capture register) Figure 6-29. Block Diagram of Clear & Start Mode Entered by TI000 Pin Valid ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-30. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input (CR000: Capture Register, CR010: Capture Register) (2/3) (b) TOC00 = 13H, PRM00 = C0H, CRC00 = 05H, TMC00 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 Figure 6-30. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input (CR000: Capture Register, CR010: Capture Register) (3/3) (c) TOC00 = 13H, PRM00 = 00H, CRC00 = 07H, TMC00 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-31. Example of Register Settings in Clear & Start Mode Entered by TI000 Pin Valid Edge Input (1/2) (a) 16-bit timer mode control register 00 (TMC00 (b) Capture/compare control ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 Figure 6-31. Example of Register Settings in Clear & Start Mode Entered by TI000 Pin Valid Edge Input (2/2) (d) Prescaler mode register 00 (PRM00) ES101 ES100 ES001 ES000 0/1 0/1 0/1 0/1 (e) ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-32. Example of Software Processing in Clear & Start Mode Entered by TI000 Pin Valid Edge Input TM00 register 0000H Operable bits 00 (TMC003, TMC002) Count clear input (TI000 pin input) Compare register ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 6.4.5 Free-running timer operation When bits 3 and 2 (TMC003 and TMC002) of 16-bit timer mode control register 00 (TMC00) are set to 01 (free- running timer mode), 16-bit timer/event counter 00 continues counting ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-34. Timing Example of Free-Running Timer Mode (CR000: Compare Register, CR010: Compare Register) TOC00 = 13H, PRM00 = 00H, CRC00 = 00H, TMC00 = 04H FFFFH TM00 register 0000H Operable bits 00 (TMC003, ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 Figure 6-36. Timing Example of Free-Running Timer Mode (CR000: Compare Register, CR010: Capture Register) TOC00 = 13H, PRM00 = 10H, CRC00 = 04H, TMC00 = 04H FFFFH TM00 register 0000H Operable bits 00 01 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (3) Free-running timer mode operation (CR000: capture register, CR010: capture register) Figure 6-37. Block Diagram of Free-Running Timer Mode (CR000: Capture Register, CR010: Capture Register) Operable bits TMC003, TMC002 Count clock Edge TI000 pin ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 Figure 6-38. Timing Example of Free-Running Timer Mode (CR000: Capture Register, CR010: Capture Register) (1/2) (a) TOC00 = 13H, PRM00 = 50H, CRC00 = 05H, TMC00 = 04H FFFFH TM00 register A 0000H Operable ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-38. Timing Example of Free-Running Timer Mode (CR000: Capture Register, CR010: Capture Register) (2/2) (b) TOC00 = 13H, PRM00 = C0H, CRC00 = 05H, TMC00 = 04H FFFFH TM00 register 0000H Operable bits ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 Figure 6-39. Example of Register Settings in Free-Running Timer Mode (1/2) (a) 16-bit timer mode control register 00 (TMC00 (b) Capture/compare control register 00 (CRC00 (c) ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-39. Example of Register Settings in Free-Running Timer Mode (2/2) (d) Prescaler mode register 00 (PRM00) ES101 ES100 ES001 ES000 0/1 0/1 0/1 0/1 (e) 16-bit timer counter 00 (TM00) By reading TM00, ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 Figure 6-40. Example of Software Processing in Free-Running Timer Mode FFFFH TM0n register N 0000H Operable bits 00 (TMC003, TMC002) Compare register (CR003) Compare match interrupt (INTTM000) Compare register (CR010) Compare match interrupt (INTTM010) ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.6 PPG output operation A square wave having a pulse width set in advance by CR010 is output from the TO00 pin as a PPG (Programmable Pulse Generator) signal during a cycle set by ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 Figure 6-42. Example of Register Settings for PPG Output Operation (a) 16-bit timer mode control register 00 (TMC00 (b) Capture/compare control register 00 (CRC00 (c) 16-bit ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-43. Example of Software Processing for PPG Output Operation TM00 register 0000H Operable bits 00 (TMC003, TMC002) Compare register (CR000) Compare match interrupt (INTTM000) Compare register (CR010) Compare match interrupt (INTTM010) Timer output ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 6.4.7 One-shot pulse output operation A one-shot pulse can be output by setting bits 3 and 2 (TMC003 and TMC002) of the 16-bit timer mode control register 00 (TMC00 (free-running timer mode) ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-45. Example of Register Settings for One-Shot Pulse Output Operation (1/2) (a) 16-bit timer mode control register 00 (TMC00 (b) Capture/compare control register 00 (CRC00 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 Figure 6-45. Example of Register Settings for One-Shot Pulse Output Operation (2/2) (e) 16-bit timer counter 00 (TM00) By reading TM00, the count value can be read. (f) 16-bit capture/compare register 000 (CR000) This ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-46. Example of Software Processing for One-Shot Pulse Output Operation (1/2) FFFFH TM00 register 0000H Operable bits (TMC003, TMC002) One-shot pulse enable bit (OSPE0) One-shot pulse trigger bit (OSPT0) One-shot pulse trigger input ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 Figure 6-46. Example of Software Processing for One-Shot Pulse Output Operation (2/2) <1> Count operation start flow START Register initial setting PRM00 register, CRC00 register, TOC00 register CR000, CR010 registers, port setting TMC003, TMC002 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.8 Pulse width measurement operation TM00 can be used to measure the pulse width of the signal input to the TI000 and TI010 pins. Measurement can be accomplished by operating the 16-bit timer/event counter ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 A pulse width can be measured in the following three ways. Measuring the pulse width by using two input signals of the TI000 and TI010 pins (free-running timer mode) Measuring the pulse width by ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (2) Measuring the pulse width by using one input signal of the TI000 pin (free-running mode) Set the free-running timer mode (TMC003 and TMC002 = 01). The count value of TM00 is captured to ...