AU80610004653AAS LBMG

Manufacturer Part NumberAU80610004653AAS LBMG
DescriptionMPU, ATOM PROCESSOR, N450, FC-BGA8
ManufacturerIntel
SeriesATOM - N400
AU80610004653AAS LBMG datasheet
 


Specifications of AU80610004653AAS LBMG

Core Size64bitCpu Speed1.66GHz
Digital Ic Case StyleBGANo. Of Pins559
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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Intel® Atom™ Processor N400 Series
Datasheet– Volume 2
This is volume 2 of 2. Refer to Document Ref# 322847 for Volume 1
April 2010
Revision 002
Document Number: 322848-002

AU80610004653AAS LBMG Summary of contents

  • Page 1

    ... Intel® Atom™ Processor N400 Series Datasheet– Volume 2 This is volume Refer to Document Ref# 322847 for Volume 1 April 2010 Revision 002 Document Number: 322848-002 ...

  • Page 2

    ... The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Intel, [include any Intel trademarks which are used in this document] and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. ...

  • Page 3

    Contents 1 Processor Configuration Registers ........................................................................... 10 1.1 Register Terminology ......................................................................................... 10 1.2 System Address Map.......................................................................................... 12 1.2.1 Legacy Address Range ............................................................................ 14 1.2.2 Main Memory Address Range ( TOLUD)........................................... 18 1.2.3 PCI Memory Address Range (TOLUD – ...

  • Page 4

    TOLUD - Top of Low Usable DRAM.............................................................65 1.5.36 ERRSTS - Error Status .............................................................................66 1.5.37 ERRCMD - Error Command.......................................................................68 1.5.38 SMICMD - SMI Command.........................................................................69 1.5.39 SKPD - Scratchpad Data ..........................................................................70 1.5.40 CAPID0 - Capability Identifier ...................................................................70 1.6 MCHBAR ...........................................................................................................74 1.6.1 ...

  • Page 5

    DMILCTL - DMI Link Control ................................................................... 118 1.7.20 DMILSTS - DMI Link Status.................................................................... 119 1.8 EPBAR ........................................................................................................... 119 1.8.1 EPESD - EP Element Self Description ....................................................... 120 1.8.2 EPLE1D - EP Link Entry 1 Description ...................................................... 121 1.8.3 EPLE1A ...

  • Page 6

    CLS - Cache Line Size............................................................................ 155 1.10.8 MLT2 - Master Latency Timer ................................................................. 156 1.10.9 HDR2 - Header Type ............................................................................. 156 1.10.10MMADR - Memory Mapped Range Address................................................ 157 1.10.11SVID2 - Subsystem Vendor Identification................................................. 157 1.10.12SID2 - Subsystem Identification ............................................................. ...

  • Page 7

    Tables 1-1 Expansion Area Memory Segments ........................................................... 16 1-2 Extended System BIOS Area Memory Segments ......................................... 17 1-3 System BIOS Area Memory Segments ....................................................... 17 1-4 Pre-allocated Memory Example for 64-MB DRAM, 1-MB VGA, and 1-MB TSEG...................................................................................... 19 1-5 SMM ...

  • Page 8

    Revision History Revision Number 001 • Initial release 002 • Updated Section 1.6.6: Corrected the description of C0DRA[7:0] 8 Description § Revision Date December 2009 April 2010 Datasheet ...

  • Page 9

    Datasheet 9 ...

  • Page 10

    ... Processor Configuration Registers This is the volume-2 of Intel intended to be distributed as part of the complete document. This document provides register information for Intel Note: Throughout this document, Intel processor and Intel 1.1 Register Terminology The following table shows the register-related terminology that is used in this document ...

  • Page 11

    Processor Configuration Registers Item RW1C-S Read/Write 1 to Clear/Sticky bit(s). These bits can be read. Internal events may set this bit. A software write of 1 clears (sets to 0) the corresponding bit(s) and a write of 0 has no ...

  • Page 12

    Item RW-O-S Read/Write Once/Sticky bit(s). Reads prior to the first write return the default value. The first write after cold reset stores any value written. Any subsequent write to this bit field is ignored. All subsequent reads return the first ...

  • Page 13

    Processor Configuration Registers The Address Map includes a number of programmable ranges: 1. Device 0: • PXPEPBAR – Egress port registers. Necessary for setting up VC1 as an isochronous channel with fixed arbitration. (4KB window) • MCHBAR – Memory mapped ...

  • Page 14

    The rules for the above programmable ranges are: • ALL of these ranges MUST be unique and NON-OVERLAPPING the BIOS or system designers' responsibility to limit memory population so that adequate PCI, High BIOS, and APIC memory space ...

  • Page 15

    Processor Configuration Registers Figure 1-2. DOS Legacy Address Range 1.2.1.1 DOS Range (0h – 9_FFFFh) The DOS area is 640 KB (0000_0000h – 0009_FFFFh) in size and is always mapped to the main memory controlled by the Integrated Memory Controller ...

  • Page 16

    Compatible SMRAM Address Range (A_0000h-B_FFFFh) When compatible SMM space is enabled, SMM-mode CPU accesses to this range are routed to physical system DRAM at 000A 0000h - 000B FFFFh. Non-SMM-mode CPU accesses to this range are considered to be ...

  • Page 17

    Processor Configuration Registers 1.2.1.4 Extended System BIOS Area (E_0000h-E_FFFFh) This 64-KB area (000E_0000h – 000E_FFFFh) is divided into four, 16-KB segments. Each segment can be assigned independent read and write attributes so it can be mapped either to main DRAM ...

  • Page 18

    Main Memory Address Range ( TOLUD) This address range extends from the top of physical memory that is permitted to be accessible by the IMC (as programmed in the TOLUD register). All accesses to ...

  • Page 19

    Processor Configuration Registers Video accelerators originally used this hole also used for validation by customer teams for some of their test cards. That is why it is being supported. There is no inherent BIOS request for the 15-MB ...

  • Page 20

    PCI Memory Address Range (TOLUD – 4 GB) This address range, from the top of physical memory (top of addressable memory space supported by the IMC is normally mapped to the DMI Interface. Exceptions to this ...

  • Page 21

    Processor Configuration Registers Figure 1-4. PCI Memory Address Range FFFF_FFFFh FFE0_0000h FEF0_0000h FEE0_0000h FED0_0000h FEC8_0000h FEC0_0000h F000_0000h E000_0000h 1.2.3.1 APIC Configuration Space (FEC0_0000h-FECF_FFFFh) This range is reserved for APIC configuration space which includes the default I/O APIC configuration space from ...

  • Page 22

    FECF_FFFFh range so that one MTRR can be programmed for the Local and I/O APICs. The I/O APIC(s) usually reside in the ICH portion of the chip set stand-alone component(s). I/O APIC units ...

  • Page 23

    Processor Configuration Registers GMADR is a Prefetchable range in order to apply USWC attribute (from the processor point of view) to that range. The USWC attribute is used by the processor for write combining. 1.2.4.1 Graphics Register Ranges This section ...

  • Page 24

    Figure 1-5. Graphics Register Memory and I/O Map Note: Some Overlay registers are double- buffered with an additional address range in graphics memory. . I/O Space Map (Standard graphics locations) VGA and Ext. VGA Registers 24 Processor Configuration Registers Memory ...

  • Page 25

    Processor Configuration Registers 1.2.5 System Management Mode (SMM) System Management Mode uses main memory for System Management RAM (SMM RAM). The processor supports: Compatible SMRAM (C_SMRAM), High Segment (HSEG), and Top of Memory Segment (TSEG). System Management RAM space provides ...

  • Page 26

    Table 1-5. SMM Space Definition Summary SMM Space Enabled Compatible (C) High (H) TSEG (T) 1.2.5.2 SMM Space restrictions If any of the following conditions are violated, the results of SMM accesses are unpredictable and may cause the system to ...

  • Page 27

    Processor Configuration Registers access to only SMM mode accesses. The D_CLS bit causes SMM data accesses to be forwarded to the DMI or PCI Express. The SMM software can use this bit to write to video memory while running SMM ...

  • Page 28

    DMI Interface read accesses to the GMADR range are not supported therefore will have no address translation concerns. DMI Interface reads to GMADR will be remapped to address 000C_0000h. The read will complete with UR (unsupported request) completion status. GTT ...

  • Page 29

    Processor Configuration Registers The processor responds to I/O cycles initiated on DMI with a UR status. Upstream I/O cycles and configuration cycles should never occur. If one does occur, the request will route as a read to memory address 0h ...

  • Page 30

    ... When a “Reserved” register location is read, a zero value is returned. (“Reserved” registers can be 8-, 16-, or 32-bit in size). Writes to “Reserved” registers have no effect on the CPU. Registers that are marked as “Intel Reserved” must not be modified by system software. Writes to “Intel Reserved” registers may cause system failure. Reads to “ ...

  • Page 31

    Processor Configuration Registers Table 1-8. Device 0 Function 0 Register Summary (Sheet Register Name Register Symbol PCI Status PCISTS Revision RID Identification Class Code CC Master Latency MLT Timer Header Type HDR Subsystem Vendor SVID Identification Subsystem ...

  • Page 32

    Table 1-8. Device 0 Function 0 Register Summary (Sheet Register Name Register Symbol Legacy Access LAC Control Remap Base REMAPBASE Address Register Remap Limit REMAPLIMIT Address Register System SMRAM Management RAM Control Extended System ESMRAMC Management RAM ...

  • Page 33

    ... Default RST/ Value PWR Device Identification Number (DID) Identifier assigned to the processor core/ primary PCI device. Intel Reserved Text: A010h Core Bits 6:4 of this field are actually determined by fuses, which allows unique sets of Device IDs to be used for different product SKUs. ...

  • Page 34

    PCICMD - PCI Command B/D/F/Type: Address Offset: Default Value: Access: Size: Since processor Device 0 does not physically reside on PCI_A many of the bits are not implemented. Bit Access 15: ...

  • Page 35

    Processor Configuration Registers Bit Access Datasheet (Sheet Default RST/ Value PWR Parity Error Enable (PERRE) Controls whether or not the Master Data Parity ...

  • Page 36

    PCISTS - PCI Status B/D/F/Type: Address Offset: Default Value: Access: Size: This status register reports the occurrence of error events on Device 0's PCI interface. Since the processor Device 0 does not physically reside on PCI_A many of the ...

  • Page 37

    Processor Configuration Registers Bit Access 10 RWC 2:0 RO Datasheet (Sheet Default RST/ Value PWR DEVSEL Timing (DEVT): These bits are hardwired to “00”. Writes ...

  • Page 38

    RID - Revision Identification B/D/F/Type: Address Offset: Default Value: Access: Size: This register contains the revision number of the processor Device 0. These bits are read only and writes to this register have no effect. Bit Access 7:0 RO ...

  • Page 39

    Processor Configuration Registers Bit Access 7:0 RO 1.5.7 MLT - Master Latency Timer B/D/F/Type: Address Offset: Default Value: Access: Size: Device 0 in the processor is not a PCI master. Therefore this register is not implemented. Bit Access 7:0 RO ...

  • Page 40

    SVID - Subsystem Vendor Identification B/D/F/Type: Address Offset: Default Value: Access: Size: This value is used to identify the vendor of the subsystem. Bit Access 15:0 RW-O 1.5.10 SID - Subsystem Identification B/D/F/Type: Address Offset: Default Value: Access: Size: ...

  • Page 41

    Processor Configuration Registers 1.5.11 CAPPTR - Capabilities Pointer B/D/F/Type: Address Offset: Default Value: Access: Size: The CAPPTR provides the offset that is the pointer to the location of the first device capability in the capability list. Bit Access 7:0 RO ...

  • Page 42

    Bit Access 63:36 RO 35:12 RW-L 11 RW-L 42 Processor Configuration Registers Default RST/ Value PWR 0000000h Reserved Core 000000h PCI Express Egress Port MMIO Base Address (PXPEPBAR): This field corresponds to bits the ...

  • Page 43

    Processor Configuration Registers 1.5.13 MCHBAR - Processor Memory Mapped Register Range Base B/D/F/Type: Address Offset: Default Value: Access: Size: This is the base address for the processor Memory Mapped Configuration space. There is no physical memory within this 16KB window ...

  • Page 44

    GGC - Processor Graphics Control Register B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access Default Value 15:10 RO 00h 9:8 RW-L 0h 7:4 RW-L 0011b 3:2 RO 00b 44 0/0/0/PCI 52-53h 0030h RW- bits RST/ PWR ...

  • Page 45

    Processor Configuration Registers Bit Access Default Value 1 RW 1.5.15 DEVEN - Device Enable B/D/F/Type: Address Offset: Default Value: Access: Size: Allows for enabling/disabling of PCI devices and functions that are within the processor. The table ...

  • Page 46

    Bit Access 3 RW-L 2 1.5.16 PCIEXBAR - PCI Express Register Range Base Address B/D/F/Type: Address Offset: Default Value: Access: Size: This is the base address for the PCI Express configuration space. This window of addresses contains ...

  • Page 47

    Processor Configuration Registers reserved above TOLUD) is not greater than the 64-bit addressable limit of 64GB. In general system implementation and number of PCI/PC Express/PCI-X buses supported in the hierarchy will dictate the length of the region. Bit Access Default ...

  • Page 48

    Bit Access Default Value 25:3 RO 000000h 2:1 RW-L-K 00b 0 RW-L 0b 1.5.17 DMIBAR - Root Complex Register Range Base Address B/D/F/Type: Address Offset: Default Value: Access: Size: This is the base address for the Root Complex configuration space. ...

  • Page 49

    Processor Configuration Registers Bit Access 63:36 RO 35:12 RW-L 11 RW-L 1.5.18 PAM0 - Programmable Attribute Map 0 B/D/F/Type: Address Offset: Default Value: Access: Size: This register controls the read, write, and shadowing attributes of the BIOS area ...

  • Page 50

    For these reasons the following critical restriction is placed on the programming of the PAM regions: At the time that a DMI accesses to the PAM region may occur, the targeted PAM segment must be programmed to be both readable ...

  • Page 51

    Processor Configuration Registers Bit Access 5:4 RW-L 3:2 RO 1:0 RW-L Datasheet Default RST/ Value PWR 0C4000-0C7FFF Attribute (HIENABLE): This field controls the steering of read and write cycles that address the BIOS area from 0C4000 to 0C7FFF. 00: DRAM ...

  • Page 52

    PAM2 - Programmable Attribute Map 2 B/D/F/Type: Address Offset: Default Value: Access: Size: This register controls the read, write, and shadowing attributes of the BIOS areas from 0C8000h- 0CFFFFh. Bit Access 7:6 RO 5:4 RW-L 3:2 RO 1:0 RW-L ...

  • Page 53

    Processor Configuration Registers 1.5.21 PAM3 - Programmable Attribute Map 3 B/D/F/Type: Address Offset: Default Value: Access: Size: This register controls the read, write, and shadowing attributes of the BIOS areas from 0D0000h- 0D7FFFh. Bit Access 7:6 RO 5:4 RW-L 3:2 ...

  • Page 54

    PAM4 - Programmable Attribute Map 4 B/D/F/Type: Address Offset: Default Value: Access: Size: This register controls the read, write, and shadowing attributes of the BIOS areas from 0D8000h- 0DFFFFh. Bit Access 7:6 RO 5:4 RW-L 3:2 RO 1:0 RW-L ...

  • Page 55

    Processor Configuration Registers 1.5.23 PAM5 - Programmable Attribute Map 5 B/D/F/Type: Address Offset: Default Value: Access: Size: This register controls the read, write, and shadowing attributes of the BIOS areas from 0E0000h- 0E7FFFh. Bit Access 7:6 RO 5:4 RW-L 3:2 ...

  • Page 56

    PAM6 - Programmable Attribute Map 6 B/D/F/Type: Address Offset: Default Value: Access: Size: This register controls the read, write, and shadowing attributes of the BIOS areas from 0E8000h- 0EFFFFh. Bit Access 7:6 RO 5:4 RW-L 3:2 RO 1:0 RW-L ...

  • Page 57

    Processor Configuration Registers 1.5.25 LAC - Legacy Access Control B/D/F/Type: Address Offset: Default Value: Access: Size: This 8-bit register controls a fixed DRAM hole from 15-16 MB. Bit Access 7 RW-L 6:0 RO 1.5.26 REMAPBASE - Remap Base Address Register ...

  • Page 58

    REMAPLIMIT - Remap Limit Address Register B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 15:10 RO 9:0 RW-L 1.5.28 SMRAM - System Management RAM Control B/D/F/Type: Address Offset: Default Value: Access: Size: The SMRAMC register controls how accesses ...

  • Page 59

    Processor Configuration Registers Bit Access Default Value RW-L RW-L 0b 2:0 RO 010b Datasheet RST/ Description PWR SMM Space Closed (D_CLS): When D_CLS = 1 SMM space DRAM is not accessible to data references, ...

  • Page 60

    ESMRAMC - Extended System Management RAM Control B/D/F/Type: Address Offset: Default Value: Access: Size: The Extended SMRAM register controls the configuration of Extended SMRAM space. The Extended SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM memory space that is ...

  • Page 61

    Processor Configuration Registers Bit Access Default Value 2:1 RW-L 00b 0 RW-L 0b 1.5.30 TOM - Top of Memory B/D/F/Type: Address Offset: Default Value: Access: Size: This Register contains the size of physical memory. BIOS determines the memory size reported ...

  • Page 62

    TOUUD - Top of Upper Usable DRAM B/D/F/Type: Address Offset: Default Value: Access: Size: This 16 bit register defines the Top of Upper Usable DRAM. Configuration software must set this value to TOM minus all EP stolen memory if ...

  • Page 63

    Processor Configuration Registers 1.5.32 GBSM - Graphics Base of Stolen Memory B/D/F/Type: Address Offset: Default Value: Access: Size: This register contains the base address of graphics data stolen DRAM memory. BIOS determines the base of graphics data stolen memory by ...

  • Page 64

    Note: This register is locked and becomes Read Only when the D_LCK bit in the SMRAM register is set. Bit Access 31:20 RW-L 19:0 RO 1.5.34 TSEGMB - TSEG Memory Base B/D/F/Type: Address Offset: Default Value: Access: Size: This register ...

  • Page 65

    Processor Configuration Registers 1.5.35 TOLUD - Top of Low Usable DRAM B/D/F/Type: Address Offset: Default Value: Access: Size: This 16 bit register defines the Top of Low Usable DRAM. TSEG, GTT Graphics Memory and Graphics Stolen Memory are within the ...

  • Page 66

    Default Bit Access Value 15:4 RW-L 001h 3:0 RO 0000b 1.5.36 ERRSTS - Error Status B/D/F/Type: Address Offset: Default Value: Access: Size: This register is used to report various error conditions via the SERR DMI messaging mechanism. An SERR DMI ...

  • Page 67

    Processor Configuration Registers Bit Access 15: RWC/S 11 RWC RWC RWC/S 6 Datasheet Default RST/PWR Value 000b Core Reserved Processor Software Generated Event for SMI (GSGESMI): 0b ...

  • Page 68

    ERRCMD - Error Command B/D/F/Type: Address Offset: Default Value: Access: Size: This register controls the processor responses to various system errors. Since the processor does not have an SERRB signal, SERR messages are passed from the processor to the ...

  • Page 69

    Processor Configuration Registers Bit Access 1.5.38 SMICMD - SMI Command B/D/F/Type: Address Offset: Default Value: Access: Size: This register enables various errors to generate an SMI DMI special cycle. When an error ...

  • Page 70

    SKPD - Scratchpad Data B/D/F/Type: Address Offset: Default Value: Access: Size: This register holds 32 writable bits with no functionality behind them for the convenience of BIOS and graphics drivers. Bit Access 31:0 RW 1.5.40 CAPID0 - ...

  • Page 71

    Processor Configuration Registers Bit Access Datasheet Default RST/PWR Value Internal Graphics Disable (INTGFXDIS): 0: There is a graphics engine within the processor. Internal Graphics Device (Device #2) is enabled and all of ...

  • Page 72

    Bit Access Processor Configuration Registers Default RST/PWR Value Enhanced Addressing XOR mode for DDR disable (EAXMDD): Controls whether the Memory Controller is capable of using Enhanced Addressing XOR modes to optimize ...

  • Page 73

    Processor Configuration Registers Bit Access 38 RO 37: 33:31 RO 30:28 RO 27:24 RO 23:16 RO 15:8 RO 7:0 RO Datasheet Default RST/PWR Value 0b Core Reserved 000b Core Reserved 0b Core Reserved DDR Frequency Capability (DDRFC): ...

  • Page 74

    MCHBAR Table 1-9. MCHBAR Register Summary (Sheet Register Name Register Symbol Channel Decode Misc CHDECMISC Channel 0 DRAM Rank C0DRB0 Boundary Address 0 Channel 0 DRAM Rank C0DRB1 Boundary Address 1 Channel 0 DRAM Rank C0DRB2 ...

  • Page 75

    Processor Configuration Registers Table 1-9. MCHBAR Register Summary (Sheet Register Name Register Symbol Thermal Sensor TSTTP Temperature Trip Point DAC/GPIO Control DACGIOCTRL1 Register 1 Power Management PMCFG Configuration Power Management PMSTS Status 1.6.1 CHDECMISC - Channel Decode ...

  • Page 76

    Bit Access Default Value 1:0 RO 00b 1.6.2 C0DRB0 – Channel 0 DRAM Rank Boundary Address 0 B/D/F/Type: Address Offset: Default Value: Access: Size: The DRAM Rank Boundary Registers define the upper boundary address of each DRAM rank with a ...

  • Page 77

    Processor Configuration Registers 1.6.3 C0DRB1 - Channel 0 DRAM Rank Boundary Address 1 B/D/F/Type: Address Offset: Default Value: Access: Size: Note: See C0DRB0 Bit Access Default Value 15:10 RO 000000b 9:0 RW-L 000h 1.6.4 C0DRB2 - Channel 0 DRAM Rank ...

  • Page 78

    C0DRB3 - Channel 0 DRAM Rank Boundary Address 3 B/D/F/Type: Address Offset: Default Value: Access: Size: Note: See C0DRB0 Bit Access Default Value 15:10 RO 000000b 9:0 RW-L 000h 1.6.6 C0DRA01 - Channel 0 DRAM Rank 0,1 Attribute B/D/F/Type: ...

  • Page 79

    Processor Configuration Registers DRA Cfg Tech 0 256Mb 1 256Mb 2 512Mb 3 512Mb 1Gb 7 1Gb 8 2Gb 9 2Gb Bit Access Default Value 15:8 RW-L 00h 7:0 RW-L 00h 1.6.7 C0DRA23 - Channel 0 DRAM ...

  • Page 80

    Bit Access 15:8 RW-L 7:0 RW-L 1.6.8 C0CYCTRKPCHG - Channel 0 CYCTRK PCHG B/D/F/Type: Address Offset: Default Value: Access: Size: Channel 0 CYCTRK Precharge Registers. Default Bit Access Value 15:11 RO 00000b 10:6 RW 00000b 5:2 RW 0000b 1:0 RW ...

  • Page 81

    Processor Configuration Registers 1.6.9 C0CYCTRKACT - Channel 0 CYCTRK ACT B/D/F/Type: Address Offset: Default Value: Access: Size: Channel 0 CYCTRK Activate Registers. Default Bit Access Value 31: 27:22 RW 000000b 20:17 RW 0000b 16:13 RW ...

  • Page 82

    Default Bit Access Value 8:0 RW 000000000 b 1.6.10 C0CYCTRKWR - Channel 0 CYCTRK WR B/D/F/Type: Address Offset: Default Value: Access: Size: Channel 0 CYCTRK WR Registers. Default Bit Access Value 15 ...

  • Page 83

    Processor Configuration Registers 1.6.11 C0CYCTRKRD - Channel 0 CYCTRK READ B/D/F/Type: Address Offset: Default Value: Access: Size: Channel 0 CYCTRK RD Registers. Default Bit Access Value 23:21 RO 000b 20: 16:12 RW 00000b 11:8 RW 0000b 7:4 RW ...

  • Page 84

    C0CYCTRKREFR - Channel 0 CYCTRK REFR B/D/F/Type: Address Offset: Default Value: Access: Size: Channel 0 CYCTRK Refresh Registers. Default Bit Access Value 15:13 RO 000b 12:9 RW 0000b 8:0 RW 000000000 b 1.6.13 C0CKECTRL - Channel 0 CKE Control ...

  • Page 85

    Processor Configuration Registers Default Bit Access Value 26:24 RW 000b RW-L 0b 19:17 RW 000b 15:14 RO 00b 13:10 RW 0010b 9:1 RW 000000000 ...

  • Page 86

    C0REFRCTRL - Channel 0 DRAM Refresh Control B/D/F/Type: Address Offset: Default Value: Access: Size: Settings to configure the DRAM refresh controller. Default Bit Access Value 46:44 RW 010b 43:38 RW 010000b 37:32 RW 011000b 31:27 RW ...

  • Page 87

    Processor Configuration Registers Default Bit Access Value 21:20 RW 00b 19:18 RW 00b 17:16 RW 00b 15:14 RW 00b Datasheet RST/PWR Core All Rank Refresh (ALLRKREF): This configuration bit enables (by ...

  • Page 88

    Default Bit Access Value 13:0 RW 001100001 10000b 1.6.15 C0ODTCTRL - Channel 0 ODT Control B/D/F/Type: Address Offset: Default Value: Access: Size: ODT controls Default Bit Access Value 31:12 RO 00000h 11:8 RW 0000b 7:4 RW 0000b 3:0 RW 0000b ...

  • Page 89

    Processor Configuration Registers 1.6.16 C0GTEW - Channel 0 Memory Controller Throttling Event Weights. B/D/F/Type: Address Offset: Default Value: Access: Size: Programmable Event weights that are input into the averaging filter. Each Event weight is an normalized 8 bit value that ...

  • Page 90

    ... Reserved Core Throttle Test Mode Enable (TTME): This bit is used to shorten the time window over which the filter makes its calculations. 0: Normal Operation 1: Filter Time Constant = 27 This bit is Intel Reserved Core Reserved Core Memory Controller Bandwidth Based Throttling Enable (GBBTE): 0: Weighted Average - Bandwidth (WAB) is not used for throttling ...

  • Page 91

    Processor Configuration Registers Default Bit Access Value 18:16 RW-L 000b 15:8 RW-L 00h 7:0 RW-L 00h 1.6.18 C0DTPEW - Channel 0 DRAM Rank Throttling Passive Event B/D/F/Type: Address Offset: Default Value: Access: Size: Programmable Event weights are input into the ...

  • Page 92

    Default Bit Access Value 31:24 RW-L 00h 23:16 RW-L 00h 15:8 RW-L 00h 7:0 RW-L 00h 1.6.19 C0DTAEW - Channel 0 DRAM Rank Throttling Active Event B/D/F/Type: Address Offset: Default Value: Access: Size: Programmable Event weights are input into the ...

  • Page 93

    Processor Configuration Registers Default Bit Access Value 63:48 RO 0000h 47:40 RW-L 00h 39:32 RW-L 00h 31:24 RW-L 00h 23:16 RW-L 00h 15:8 RW-L 00h 7:0 RW-L 00h Datasheet RST/PWR Core Reserved Core Read Weight (RDW): This value is input ...

  • Page 94

    ... Core Throttle Test Mode Enable (TTME): This bit is used to shorten the time window over which the filter averages. 0: Normal Operation 1: Filter Time Constant = 2^7 This bit is Intel Reserved Core DRAM Bandwidth Based Throttling Enable (DBBTE): 0: Bandwidth Threshold (WAB) is not used for throttling. ...

  • Page 95

    Processor Configuration Registers Default Bit Access Value 15:8 RW-L 00h 7:0 RW-L 00h 1.6.21 TSC1 - Thermal Sensor Control 1 B/D/F/Type: Address Offset: Default Value: Access: Size: This register controls the operation of the thermal sensor. Bits 7:1 of this ...

  • Page 96

    Default Bit Access Value 5:2 RW-P 0000b 1 RW-L RS- Processor Configuration Registers RST/PWR Core Digital Hysteresis Amount (DHA): This bit determines whether no offset, 1 LSB, 2... 15 is used for hysteresis for the trip ...

  • Page 97

    Processor Configuration Registers 1.6.22 TSS - Thermal Sensor Status B/D/F/Type: Address Offset: Default Value: Access: Size: This read only register provides trip point and other status of the thermal sensor. All bits in this register are reset to their defaults ...

  • Page 98

    TR - Thermometer Read B/D/F/Type: Address Offset: Default Value: Access: Size: This register generally provides the calibrated current temperature from the thermometer circuit when the Thermometer mode is enabled. See the temperature tables for the temperature calculations. All bits ...

  • Page 99

    Processor Configuration Registers 1.6.24 TSTTP - Thermal Sensor Temperature Trip Point B/D/F/Type: Address Offset: Default Value: Access: Size: This register: 1. Sets the target values for the trip points in thermometer mode. See also TST[Direct DAC Connect Test Enable]. 2. ...

  • Page 100

    DACGIOCTRL1 - DAC/GPIO Control Register 1 B/D/F/Type: Address Offset: Default Value: Access: Size: Default Bit Access Value 31:28 RO 0000b 23:0 RW 020280h 1.6.26 PMCFG - Power ...

  • Page 101

    Processor Configuration Registers Default Bit Access Value 29:5 RO 0000000 1:0 RO 00b Datasheet RST/PWR Core Multiple Req C2/C0 Enable (MRC2C0E): 0: The processor does not re-issue ...

  • Page 102

    PMSTS - Power Management Status B/D/F/Type: Address Offset: Default Value: Access: Size: This register is Reset by PWROK only. Default Bit Access Value 31:9 RO 000000h 8 RWC/P 0b 7:1 RO 00h 0 RWC/P 0b 102 Processor Configuration Registers ...

  • Page 103

    Processor Configuration Registers 1.7 DMIBAR Register Register Name Symbol DMI Virtual DMIVCECH Channel Enhanced Capability DMI Port VC DMIPVCCAP1 Capability Register 1 DMI Port VC DMIPVCCAP2 Capability Register 2 DMI Port VC DMIPVCCTL Control DMI VC0 DMIVC0RCAP Resource Capability DMI ...

  • Page 104

    Register Register Name Symbol DMI Root DMIRCILCECH Complex Internal Link Control DMI Link DMILCAP Capabilities DMI Link DMILCTL Control DMI Link Status DMILSTS 1.7.1 DMIVCECH - DMI Virtual Channel Enhanced Capability B/D/F/Type: Address Offset: Default Value: Access: Size: Indicates DMI ...

  • Page 105

    Processor Configuration Registers 1.7.2 DMIPVCCAP1 - DMI Port VC Capability Register 1 B/D/F/Type: Address Offset: Default Value: Access: Size: Describes the configuration of PCI Express Virtual Channels associated with this port. Default Bit Access Value 31:7 RO 0000000h 6:4 RO ...

  • Page 106

    DMIPVCCTL - DMI Port VC Control B/D/F/Type: Address Offset: Default Value: Access: Size: Default Bit Access Value 15:4 RO 000h 3:1 RW 000b 1.7.5 DMIVC0RCAP - DMI VC0 Resource Capability B/D/F/Type: Address Offset: Default Value: Access: ...

  • Page 107

    Processor Configuration Registers Default Bit Access Value 7:0 RO 01h 1.7.6 DMIVC0RCTL0 - DMI VC0 Resource Control B/D/F/Type: Address Offset: Default Value: Access: Size: Controls the resources associated with PCI Express Virtual Channel 0. Default Bit Access Value 31 RO ...

  • Page 108

    Default Bit Access Value 1.7.7 DMIVC0RSTS - DMI VC0 Resource Status B/D/F/Type: Address Offset: Default Value: Access: Size: Reports the Virtual Channel specific status. Default Bit Access Value 15:2 RO 0000h ...

  • Page 109

    Processor Configuration Registers 1.7.8 DMIVC1RCAP - DMI VC1 Resource Capability B/D/F/Type: Address Offset: Default Value: Access: Size: Default Bit Access Value 31:24 RO 00h 22:16 RO 00h 14:8 RO 00h 7:0 RO 01h 1.7.9 ...

  • Page 110

    Default Bit Access Value 30: 26:24 RW 001b 23: 19:17 RW 000b 16:8 RO 000h 7:1 RW 00h 110 Processor Configuration Registers RST/PWR Virtual Channel 1 Enable (VC1E): 0: Virtual ...

  • Page 111

    Processor Configuration Registers 1.7.10 DMIVC1RSTS - DMI VC1 Resource Status B/D/F/Type: Address Offset: Default Value: Access: Size: Reports the Virtual Channel specific status. Default Bit Access Value 15:2 RO 0000h Datasheet 0/0/0/DMIBAR 26-27h 0002h ...

  • Page 112

    DMIRCLDECH B/D/F/Type: Address Offset: Default Value: Access: Size: This capability declares links from the respective element to other elements of the root complex component to which it belongs and to an element in another root complex component. See PCI ...

  • Page 113

    Processor Configuration Registers Default Bit Access Value 31:24 RO 01h 23:16 RWO 00h 15:8 RO 02h 7 3 1.7.13 DMILE1D - DMI Link Entry 1 Description B/D/F/Type: Address Offset: Default Value: Access: Size: First part of ...

  • Page 114

    Default Bit Access Value 23:16 RWO 00h 15:2 RWO 0000h 1.7.14 DMILE1A - DMI Link Entry 1 Address B/D/F/Type: Address Offset: Default Value: Access: Size: Second part of a Link Entry which declares an ...

  • Page 115

    Processor Configuration Registers 1.7.15 DMILE2D - DMI Link Entry 2 Description B/D/F/Type: Address Offset: Default Value: Access: Size: First part of a Link Entry which declares an internal link to another Root Complex Element. Default Bit Access Value 31:24 RO ...

  • Page 116

    DMILE2A - DMI Link Entry 2 Address B/D/F/Type: Address Offset: Default Value: Access: Size: Second part of a Link Entry which declares an internal link to another Root Complex Element. Bit Access 63:36 RO 35:12 RWO 11:0 RO 1.7.17 ...

  • Page 117

    Processor Configuration Registers 1.7.18 DMILCAP - DMI Link Capabilities B/D/F/Type: Address Offset: Default Value: Access: Size: Indicates DMI specific capabilities. Default Bit Access Value 31:18 RO 0000h 17:15 RWO 010b 14:12 RWO 010b Datasheet 0/0/0/DMIBAR 84-87h 00012C41h RO; RWO; 32 ...

  • Page 118

    Default Bit Access Value 11:10 RO 11b 9:4 RO 04h 3 1.7.19 DMILCTL - DMI Link Control B/D/F/Type: Address Offset: Default Value: Access: Size: Allows control of DMI. Default Bit Access Value 15:8 RO 00h ...

  • Page 119

    Processor Configuration Registers 1.7.20 DMILSTS - DMI Link Status B/D/F/Type: Address Offset: Default Value: Access: Size: Indicates DMI status. Default Bit Access Value 15:10 RO 00h 9:4 RO 00h 3 1.8 EPBAR Table 1-10.EPBAR Register Summary Register Name ...

  • Page 120

    EPESD - EP Element Self Description B/D/F/Type: Address Offset: Default Value: Access: Size: Provides information about the root complex element containing this Link Declaration Capability. Bit Access 31:24 RO 23:16 RWO 15:8 RO 7:4 RO 3:0 RO 120 Processor ...

  • Page 121

    Processor Configuration Registers 1.8.2 EPLE1D - EP Link Entry 1 Description B/D/F/Type: Address Offset: Default Value: Access: Size: First part of a Link Entry which declares an internal link to another Root Complex Element. Bit Access 31:24 RO 23:16 RWO ...

  • Page 122

    EPLE1A - EP Link Entry 1 Address B/D/F/Type: Address Offset: Default Value: Access: Size: Second part of a Link Entry which declares an internal link to another Root Complex Element. Bit Access 63:36 RO 35:12 RWO 11:0 RO 1.8.4 ...

  • Page 123

    Processor Configuration Registers Bit Access Default Value 23:16 RWO 00h 15:2 RO 0000h RWO 0b 1.8.5 EPLE2A - EP Link Entry 2 Address B/D/F/Type: Address Offset: Default Value: Access: Size: Second part of a Link Entry ...

  • Page 124

    PCI Device 2 Function 0 Table 1-11.PCI Device 2 Function 0 Registers Summary (Sheet Register Register Name Symbol Vendor VID2 Identification Device DID Identification PCI Command PCICMD2 PCI Status PCISTS2 Revision RID2 Identification Class Code CC ...

  • Page 125

    Processor Configuration Registers Table 1-11.PCI Device 2 Function 0 Registers Summary (Sheet Register Register Name Symbol Mirror of Device CAPID0 0 Capability Identifier processor MGGC Graphics Control Register Device Enable DEVEN Software SSRW Scratch Read Write Base ...

  • Page 126

    ... RO; 16 bits RST/PWR Device Identification Number (DID): This bit value Identifier assigned to the processor core/primary PCI device. Intel Reserved Text: Bits 6:4 of Core this field are actually determined by fuses, which allows unique sets of Device IDs to be used for different product SKUs. ...

  • Page 127

    Processor Configuration Registers 1.9.3 PCICMD2 - PCI Command B/D/F/Type: Address Offset: Default Value: Access: Size: This 16-bit register provides basic control over the IGD's ability to respond to PCI cycles. The PCICMD Register in the IGD disables the IGD PCI ...

  • Page 128

    Default Bit Access Value 1.9.4 PCISTS2 - PCI Status B/D/F/Type: Address Offset: Default Value: Access: Size: PCISTS is a 16-bit status register that reports the occurrence of a PCI compliant master abort and PCI ...

  • Page 129

    ... This is an 8-bit value that indicates the revision identification number for the processor Device 0. For the Core A-0 Stepping, this value is 00h. [Intel Reserved text: For the A-1 Stepping, the CRID value is 00h and the SRID value is 01h. SRID bit 7 will be set to 1 for discrete Die ...

  • Page 130

    CC - Class Code B/D/F/Type: Address Offset: Default Value: Access: Size: This register contains the device programming interface information related to the Sub- Class Code and Base Class Code definition for the IGD. This register also contains the Base ...

  • Page 131

    Processor Configuration Registers 1.9.8 MLT2 - Master Latency Timer B/D/F/Type: Address Offset: Default Value: Access: Size: The IGD does not support the programmability of the master latency timer because it does not perform bursts. Default Bit Access Value 7:0 RO ...

  • Page 132

    MMADR - Memory Mapped Range Address B/D/F/Type: Address Offset: Default Value: Access: Size: This register requests allocation for the IGD registers and instruction ports. The allocation is for 512 KB and the base address is defined by bits [31:19]. ...

  • Page 133

    Processor Configuration Registers If accesses to this IO bar is allowed then the processor claims all bit IO cycles from the CPU that falls within the 8B claimed. Default Bit Access Value 31:16 RO 0000h 15:3 ...

  • Page 134

    Default Bit Access Value 1.9.13 GTTADR - Graphics Translation Table Range Address B/D/F/Type: Address Offset: Default Value: Access: Size: This register requests allocation for Graphics Translation Table Range. The allocation is for 1 MB and the base ...

  • Page 135

    Processor Configuration Registers Default Bit Access Value 15:0 RWO 0000h 1.9.15 SID2 - Subsystem Identification B/D/F/Type: Address Offset: Default Value: Access: Size: Default Bit Access Value 15:0 RWO 0000h 1.9.16 ROMADR - Video BIOS ROM Base Address B/D/F/Type: Address Offset: ...

  • Page 136

    CAPPOINT - Capabilities Pointer B/D/F/Type: Address Offset: Default Value: Access: Size: Default Bit Access Value 7:0 RO 90h 1.9.18 INTRLINE - Interrupt Line B/D/F/Type: Address Offset: Default Value: Access: Size: Default Bit Access Value 7:0 RW 00h 136 Processor ...

  • Page 137

    Processor Configuration Registers 1.9.19 INTRPIN - Interrupt Pin B/D/F/Type: Address Offset: Default Value: Access: Size: Default Bit Access Value 7:0 RO 01h 1.9.20 MINGNT - Minimum Grant B/D/F/Type: Address Offset: Default Value: Access: Size: Default Bit Access Value 7:0 RO ...

  • Page 138

    MGGC - Processor Graphics Control Register B/D/F/Type: Address Offset: Default Value: Access: Size: Default Bit Access Value 15:10 RO 00h 9 7:4 RO 0011b 138 Processor Configuration Registers 0/2/0/PCI 52-53h 0030h RO; 16 bits RST/PWR Core Reserved ...

  • Page 139

    Processor Configuration Registers Default Bit Access Value 3:2 RO 00b 1.9.23 DEVEN - Device Enable B/D/F/Type: Address Offset: Default Value: Access: Size: Allows for enabling/disabling of PCI devices and functions that are within the ...

  • Page 140

    SSRW - Software Scratch Read Write B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 31:0 RW 1.9.25 BSM - Base of Stolen Memory B/D/F/Type: Address Offset: Default Value: Access: Size: Graphics Stolen Memory and Tseg are within DRAM ...

  • Page 141

    Processor Configuration Registers 1.9.26 HSRW - Hardware Scratch Read Write B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 15:0 RW 1.9. Message Control B/D/F/Type: Address Offset: Default Value: Access: Size: System software can modify bits in this ...

  • Page 142

    Default Bit Access Value 3:1 RO 000b 1.9. Message Address B/D/F/Type: Address Offset: Default Value: Access: Size: Default Bit Access Value 31:2 RW 00000000h 1:0 RO 00b 142 Processor Configuration Registers RST/PWR Multiple Message Capable ...

  • Page 143

    Processor Configuration Registers 1.9. Message Data B/D/F/Type: Address Offset: Default Value: Access: Size: Default Bit Access Value 15:0 RW 0000h 1.9.30 GDRST – Graphics Debug Reset B/D/F/Type: Address Offset: Default Value: Access: Size: Default Bit Access Value 7:4 ...

  • Page 144

    Default Bit Access Value 1.9.31 PMCAPID - Power Management Capabilities ID B/D/F/Type: Address Offset: Default Value: Access: Size: Default Bit Access Value 15:8 RWO 00h 7:0 RO 01h 1.9.32 PMCAP - Power Management Capabilities B/D/F/Type: Address Offset: ...

  • Page 145

    Processor Configuration Registers This register is a Mirror of Function 0 with the same read/write attributes. The hardware implements a single physical register common to both functions 0 and 1. Default Bit Access Value 15:11 RO 00h ...

  • Page 146

    Default Bit Access Value 12 7:2 RO 00h 1:0 RW 00b 1.9.34 SWSMI - Software SMI B/D/F/Type: Address Offset: Default Value: Access: Size: As long as there is the potential that DVO port legacy drivers ...

  • Page 147

    Processor Configuration Registers 1.9.35 LBB - Legacy Backlight Brightness B/D/F/Type: Address Offset: Default Value: Access: Size: Note: Please use this register to trigger ASLE interrupts with the processor. This register can be accessed by either Byte, Word, or Dword PCI ...

  • Page 148

    Default Bit Access Value 15:8 RW 00h 7:0 RW 00h 1.9.37 ASLS – ASL Storage B/D/F/Type: Address Offset: Default Value: Access: Size: This software scratch register only needs to be read/write accessible. The exact bit register usage must be worked ...

  • Page 149

    Processor Configuration Registers 1.10 PCI Device 2 Function 1 Table 1-12.PCI Device 2 Function 1 Register Summary (Sheet Register Register Name Symbol Vendor VID2 Identification Device DID2 Identification PCI Command PCICMD2 PCI Status PCISTS2 Revision RID2 Identification ...

  • Page 150

    Table 1-12.PCI Device 2 Function 1 Register Summary (Sheet Register Register Name Symbol Mirror of Fun 0 SSRW Software Scratch Read Write Mirror of Func0 BSM Base of Stolen Memory Mirror of Dev2 HSRW Func0 Hardware Scratch ...

  • Page 151

    ... Device Identification Number (DID): This bit value Identifier assigned to the processor core/primary PCI device. A012h Core Intel Reserved Text Bits 6:4 of this field are actually determined by fuses, which allows unique sets of Device IDs to be used for different product SKUs. Description Description ...

  • Page 152

    PCICMD2 - PCI Command B/D/F/Type: Address Offset: Default Value: Access: Size: This 16-bit register provides basic control over the IGD's ability to respond to PCI cycles. The PCICMD Register in the IGD disables the IGD PCI compliant master accesses ...

  • Page 153

    Processor Configuration Registers Default Bit Access Value 1.10.4 PCISTS2 - PCI Status B/D/F/Type: Address Offset: Default Value: Access: Size: PCISTS is a 16-bit status register that reports the occurrence of a PCI compliant master abort and PCI ...

  • Page 154

    ... Revision Identification Number (RID): This is an 8-bit value that indicates the revision identification number for the processor Device 0. For the A-0 Stepping, this value is 00h. [Intel Reserved text: For the A-1 Stepping, the 00h Core CRID value is 00h and the SRID value is 01h ...

  • Page 155

    Processor Configuration Registers 1.10 Class Code Register B/D/F/Type: Address Offset: Default Value: Access: Size: This register contains the device programming interface information related to the Sub- Class Code and Base Class Code definition for the IGD. This register ...

  • Page 156

    MLT2 - Master Latency Timer B/D/F/Type: Address Offset: Default Value: Access: Size: The IGD does not support the programmability of the master latency timer because it does not perform bursts. Bit Access 7:0 RO 1.10.9 HDR2 - Header Type ...

  • Page 157

    Processor Configuration Registers 1.10.10 MMADR - Memory Mapped Range Address B/D/F/Type: Address Offset: Default Value: Access: Size: This register requests allocation for the IGD registers and instruction ports. The allocation is for 512 KB and the base address is defined ...

  • Page 158

    SID2 - Subsystem Identification B/D/F/Type: Address Offset: Default Value: Access: Size: Default Bit Access Value 15:0 RO 0000h 1.10.13 ROMADR - Video BIOS ROM Base Address B/D/F/Type: Address Offset: Default Value: Access: Size: The IGD does not use a ...

  • Page 159

    Processor Configuration Registers 1.10.14 CAPPOINT - Capabilities Pointer B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 7:0 RO 1.10.15 MINGNT - Minimum Grant B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 7:0 RO 1.10.16 MAXLAT - Maximum Latency ...

  • Page 160

    Bit Access 7:0 RO 1.10.17 CAPID0 - Mirror of Device 0 Capability Identifier B/D/F/Type: Address Offset: Default Value: Access: Size: Control of bits in this register are only required for customer visible SKU differentiation. Bit Access 63:58 RO 57:55 RO ...

  • Page 161

    Processor Configuration Registers 23:16 RO 15:8 RO 7:0 RO 1.10.18 MGGC - Mirror of Dev 0 processor Graphics Control Register B/D/F/Type: Address Offset: Default Value: Access: Size: Default Bit Access Value 15:10 RO 00h 9 Datasheet 08h Core ...

  • Page 162

    Default Bit Access Value 7:4 RO 0011b 3:2 RO 00b 1.10.19 DEVEN - Device Enable B/D/F/Type: Address Offset: Default Value: Access: Size: Allows for enabling/disabling of PCI devices and functions that are within the ...

  • Page 163

    Processor Configuration Registers Default Bit Access Value 31:15 RO 00000h 13:5 RO 000h 2:1 RO 00b Datasheet RST/PWR Core Reserved Chap Enable (D7EN): 0: Bus 0 Device 7 ...

  • Page 164

    SSRW - Mirror of Fun 0 Software Scratch Read Write B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 31:0 RO 1.10.21 BSM - Mirror of Func0 Base of Stolen Memory B/D/F/Type: Address Offset: Default Value: Access: Size: Graphics ...

  • Page 165

    Processor Configuration Registers 1.10.22 HSRW - Mirror of Dev2 Func0 Hardware Scratch Read Write B/D/F/Type: Address Offset: Default Value: Access: Size: Bit Access 15:0 RO 1.10.23 PMCAPID - Mirror of Fun 0 Power Management Capabilities ID B/D/F/Type: Address Offset: Default ...

  • Page 166

    PMCAP - Mirror of Fun 0 Power Management Capabilities B/D/F/Type: Address Offset: Default Value: Access: Size: This register is a Mirror of Function 0 with the same read/write attributes. The hardware implements a single physical register common to both ...

  • Page 167

    Processor Configuration Registers 1.10.25 PMCS - Power Management Control/Status B/D/F/Type: Address Offset: Default Value: Access: Size: Default Bit Access Value 14:13 RO 00b 12 7:2 RO 00h 1:0 RW 00b Datasheet 0/2/1/PCI ...

  • Page 168

    SWSMI - Mirror of Func0 Software SMI B/D/F/Type: Address Offset: Default Value: Access: Size: As long as there is the potential that DVO port legacy drivers exist which expect this register at this address, Dev#2F0address E0h-E1h must be reserved ...

  • Page 169

    Processor Configuration Registers Default Bit Access Value 15:8 RO 00h 7:0 RO 00h 1.10.28 ASLS - ASL Storage B/D/F/Type: Address Offset: Default Value: Access: Size: This software scratch register only needs to be read/write accessible. The exact bit register usage ...

  • Page 170

    Device 2 IO Register Name MMIO Address Register MMIO Data Register 1.11.1 Index - MMIO Address Register B/D/F/Type: Address Offset: Default Value: Access: Size: MMIO_INDEX bit IO write to this port loads the offset of the MMIO ...

  • Page 171

    Processor Configuration Registers 1.11.2 Data - MMIO Data Register B/D/F/Type: Address Offset: Default Value: Access: Size: MMIO_DATA bit IO write to this port is re-directed to the MMIO register/GTT location pointed to by the MMIO-index register ...