AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 100
AU80610004653AAS LBMG
Manufacturer Part Number
AU80610004653AAS LBMG
Description
MPU, ATOM PROCESSOR, N450, FC-BGA8
Manufacturer
Intel
Series
ATOM - N400r
Datasheet
1.AU80610004653AAS_LBMG.pdf
(171 pages)
Specifications of AU80610004653AAS LBMG
Core Size
64bit
Cpu Speed
1.66GHz
Digital Ic Case Style
BGA
No. Of Pins
559
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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1.6.25
1.6.26
100
31:28
23:0
Bit
Bit
27
26
25
24
31
Access
Access
RW
DACGIOCTRL1 - DAC/GPIO Control Register 1
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
RW
RW
RW
RW
RW
PMCFG - Power Management Configuration
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
RO
Default
Value
020280h
0b
Default
Value
0000b
0b
0b
0b
0b
RST/PWR
Core
RST/PWR
Core
Core
Core
Core
Core
Core
Reset Warn Self Refresh Disable (RWSRD):
reset warn message.
reset warn message. Memory state is unchanged as a result
of a reset warn message.
In either case the IMC sends an acknowledge to chipset.
0: Memory is placed in self refresh state as a result of a
1: Memory may not be in self refresh state as a result of a
Reserved
Reserved
LCTL Input Buffer Disable (LCTLDIS):
Control GPIO Input Buffer of LCTL Clock and Data.
0 - Input Buffer is Enabled
1 - Input Buffer is Disabled
Flat Panel DDC Input Buffer Disable (LDDCDIS):
Control GPIO Input Buffer of Flat Panel DDC Clock and
Data.
0 - Input Buffer is Enabled
1 - Input Buffer is Disabled
Reserved
Reserved
0/0/0/MCHBAR
B08-B0Bh
00020280h
32 bits
0/0/0/MCHBAR
F10-F13h
00000000h
32 bits
RW; RO;
RW; RO;
Description
Processor Configuration Registers
Description
Datasheet
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