AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 113

• Manufacturer Part Number: AU80610004653AAS LBMG
• Description: MPU, ATOM PROCESSOR, N450, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - N400r

Specifications of AU80610004653AAS LBMG

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Processor Configuration Registers
1.7.13
Datasheet
31:24
23:16
15:8
7:4
3:0
31:24
Bit
Bit
RO
RWO
RO
RO
RO
RWO
Access
Access
DMILE1D - DMI Link Entry 1 Description
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
First part of a Link Entry which declares an internal link to another Root Complex
Element.
01h
00h
02h
0h
2h
00h
Default
Default
Value
Value
Core
Core
Core
Core
Core
Core
RST/PWR
RST/PWR
Port Number (PORTNUM):
Specifies the port number associated with this element
with respect to the component that contains this element.
This port number value is utilized by the egress port of the
component to provide arbitration to this Root Complex
Element.
Component ID (CID):
Identifies the physical component that contains this Root
Complex Element. BIOS Requirement: Must be initialized
according to guidelines in the PCI Express* Isochronous/
Virtual Channel Support Hardware Programming
Specification (HPS).
Number of Link Entries (NLE):
Indicates the number of link entries following the Element
Self Description. This field reports 2 (one for MCH egress
port to main memory and one to egress port belonging to
chipset on other side of internal link).
Reserved
Element Type (ETYP):
Indicates the type of the Root Complex Element. Value of 2
h represents an Internal Root Complex Link (DMI).
Target Port Number (TPN):
Specifies the port number associated with the element
targeted by this link entry (egress port of chipset). The
target port number is with respect to the component that
contains this element as specified by the target component
ID. This can be programmed by BIOS, but the default value
will likely be correct because the DMI RCRB in the chipset
will likely be associated with the default egress port for the
chipset meaning it will be assigned port number 0.
0/0/0/DMIBAR
50-53h
00000000h
32 bits
RWO; RO;
Description
Description
113