AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 12

• Manufacturer Part Number: AU80610004653AAS LBMG
• Description: MPU, ATOM PROCESSOR, N450, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - N400r

Specifications of AU80610004653AAS LBMG

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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System Address Map
The processor supports 4 GB of addressable memory space and 64 KB+3 of
addressable I/O space. There is a programmable memory address space under
the 1 MB region which is divided into regions which can be individually controlled with
programmable attributes such as Disable, Read/Write, Write Only, or Read Only.
Attribute programming is described in the Register Description section. This section
focuses on how the memory space is partitioned and what the separate memory
regions are used for. I/O address space has simpler mapping and is explained near the
end of this section.
The processor supports a maximum of 2GB of DRAM. No DRAM memory will be
accessible above 2 GB. DRAM capacity is limited by the silicon fuse. There is no
hardware lock to stop someone from inserting more memory than that is addressable.
When running in internal graphics mode, writes to GMADR range linear range are
supported. Write accesses to linear regions are supported from DMI. Write accesses to
tileX and tileY regions (defined via fence registers) are not supported from DMI.
GMADR read accesses are not supported from DMI. In the following sections, it is
assumed that all of the compatibility memory ranges reside on the DMI Interface. The
exception to this rule is VGA ranges, which may be mapped to DMI or to the internal
graphics device (IGD). In the absence of more specific references, cycle descriptions
referencing PCI should be interpreted as the DMI Interface/PCI, while cycle descriptions
referencing IGD are related to the internal graphics device. processor does not remap
APIC or any other memory spaces above TOLUD (Top of Low Usable DRAM). The TOLUD
register is set to the appropriate value by BIOS. The reclaimbase/reclaimlimit registers
remap logical accesses bound for addresses above 4G onto physical addresses that fall
within DRAM.
RW-O-S
W
W1C
Item
Read/Write Once/Sticky bit(s). Reads prior to the first write return the
default value. The first write after cold reset stores any value written. Any
subsequent write to this bit field is ignored. All subsequent reads return the
first value written. The value returns to default on cold reset. If there are
multiple RW-O or RW-O-S fields within a DWORD, they should be written all at
once (atomically) to avoid capturing an incorrect value.
Write-only. These bits may be written by software, but will always return
zeros when read. They are used for write side-effects. Any data written to
these registers cannot be retrieved.
Write 1 to Clear-only. These bits may be cleared by software by writing a 1.
Writing a 0 has no effect. The state of the bits cannot be read directly. The
states of such bits are tracked outside the CPU and all read transactions to the
address of such bits are routed to the other agent. Write transactions to these
bits go to both agents.
Definition
Processor Configuration Registers
Datasheet