AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 130
AU80610004653AAS LBMG
Manufacturer Part Number
AU80610004653AAS LBMG
Description
MPU, ATOM PROCESSOR, N450, FC-BGA8
Manufacturer
Intel
Series
ATOM - N400r
Datasheet
1.AU80610004653AAS_LBMG.pdf
(171 pages)
Specifications of AU80610004653AAS LBMG
Core Size
64bit
Cpu Speed
1.66GHz
Digital Ic Case Style
BGA
No. Of Pins
559
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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1.9.6
1.9.7
130
23:16
15:8
7:0
7:0
Bit
Bit
Access
Access
CC - Class Code
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register contains the device programming interface information related to the Sub-
Class Code and Base Class Code definition for the IGD. This register also contains the
Base Class Code and the function sub-class in relation to the Base Class Code.
CLS - Cache Line Size
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
The IGD does not support this register as a PCI slave.
RO
RO
RO
RO
Default
Default
Value
Value
03h
00h
00h
00h
RST/PWR
RST/PWR
Core
Core
Core
Core
Base Class Code (BCC):
This is an 8-bit value that indicates the base class code
for the processor. This code has the value 03h, indicating
a Display Controller.
Sub-Class Code (SUBCC):
Value will be determined based on Device 0 GGC register,
GMS and IVD fields.
00h: VGA compatible
80h: Non VGA (GMS = “0000” or IVD = “1”)
Programming Interface (PI):
00h: Hardwired as a Display controller.
Cache Line Size (CLS):
This field is hardwired to 0s. The IGD as a PCI compliant
master does not use the Memory Write and Invalidate
command and, in general, does not perform operations
based on cache line size.
0/2/0/PCI
9-Bh
030000h
24 bits
0/2/0/PCI
Ch
00h
8 bits
RO;
RO;
Processor Configuration Registers
Description
Description
Datasheet
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