AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 144

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AU80610004653AAS LBMG

Manufacturer Part Number
AU80610004653AAS LBMG
Description
MPU, ATOM PROCESSOR, N450, FC-BGA8
Manufacturer
Intel
Series
ATOM - N400r
Datasheet

Specifications of AU80610004653AAS LBMG

Core Size
64bit
Cpu Speed
1.66GHz
Digital Ic Case Style
BGA
No. Of Pins
559
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
1.9.31
1.9.32
144
15:8
7:0
Bit
Bit
0
Access
Access
RWO
RW
PMCAPID - Power Management Capabilities ID
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
PMCAP - Power Management Capabilities
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
RO
Default
Default
Value
Value
00h
01h
0b
RST/PWR
RST/PWR
FLR, Core
Core
Core
Graphics Reset Enable (GR):
Setting this bit asserts graphics-only reset. The clock
domains to be reset are determined by GRDOM.
Hardware resets this bit when the reset is complete.
Setting this bit without waiting for it to clear, is undefined
behavior.
Once this bit is set to a “1” all GFX core MMIO registers
are returned to power on default state. All Ring buffer
pointers are reset, command stream fetches are dropped
and ongoing render pipeline processing is halted, state
machines and State Variables returned to power on
default state. If the Display is reset, all display engines
are halted (garbage on screen). VGA memory is not
available, Store DWORDs and interrupts are not
guaranteed to be completed. Device #2 IO registers are
not available.
Device #2 Config registers continue to be available while
Graphics reset is asserted.
This bit is HW auto-clear.
Next Capability Pointer (NEXT_PTR):
capabilities list. BIOS is responsible for writing this to the
FLR Capability when applicable.
Capability Identifier (CAP_ID):
SIG defines this ID is 01h for power management.
This contains a pointer to the next item in the
0/2/0/PCI
D0-D1h
0001h
16 bits
0/2/0/PCI
D2-D3h
0022h
16 bits
RWO; RO
RO;
Processor Configuration Registers
Description
Description
Datasheet

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