AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 146

• Manufacturer Part Number: AU80610004653AAS LBMG
• Description: MPU, ATOM PROCESSOR, N450, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - N400r

Specifications of AU80610004653AAS LBMG

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.9.34
146
12:9
15:8
7:2
1:0
7:1
Bit
Bit
8
0
Access
Access
RW
SWSMI - Software SMI
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
As long as there is the potential that DVO port legacy drivers exist which expect this
register at this address, Dev#2 F0 address E0h-E1h must be reserved for this register.
RW
RW
RW
RO
RO
RO
Default
Default
Value
Value
00h
00b
00h
00h
0h
0b
0b
RST/PWR
RST/PWR
FLR, Core
Core
Core
Core
Core
Core
Core
Data Select (DSEL):
returns 0h when read, write operations have no effect.
PME Enable (PME_EN):
(cold) is disabled.
Reserved
Power State (PWRSTAT):
and can be used to set the IGD into a new power state. If
software attempts to write an unsupported state to this
field, write operation must complete normally on the bus,
but the data is discarded and no state change occurs. On
a transition from D3 to D0 the graphics controller is
optionally reset to initial values. Behavior of the graphics
controller in supported states is detailed in the power
management section of the BIOS specification.
Software Scratch Bits (SWSB):
Software Flag (SWF):
as return result.
processor Software SMI Event (GSSMIE):
write a “0” to clear this bit.
The IGD does not support data register. This bit always
This bit is 0 to indicate that PME# assertion from D3
This field indicates the current power state of the IGD
Used to indicate caller and SMI function desired, as well
When Set this bit will trigger an SMI. Software must
0/2/0/PCI
E0-E1h
0000h
16 bits
RW;
Bits[1:0]Power state
00:
01:
10:
11:
D0Default
D1Not Supported
D2Not Supported
D3
Processor Configuration Registers
Description
Description
Datasheet