AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 147

• Manufacturer Part Number: AU80610004653AAS LBMG
• Description: MPU, ATOM PROCESSOR, N450, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - N400r

Specifications of AU80610004653AAS LBMG

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Processor Configuration Registers
1.9.35
1.9.36
Datasheet
Note:
31:24
23:16
31:24
23:16
15:8
7:0
Bit
Bit
Access
Access
LBB - Legacy Backlight Brightness
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Please use this register to trigger ASLE interrupts with the processor.
This register can be accessed by either Byte, Word, or Dword PCI config cycles. A write
to this register will cause the Backlight Event (Display B Interrupt) if enabled
RW
RW
RW
RW
ASLE – System Display Event Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
RW
RW
Default
Default
Value
Value
00h
00h
00h
00h
00h
00h
RST/PWR
RST/PWR
Core
Core
Core
Core
Core
Core
Reserved
Reserved
LBPC Scratch Trigger1 (LBPC_SCRATCH_1):
When written, this scratch byte triggers an interrupt when
LBEE is enabled in the Pipe B Status register and the
Display B Event is enabled in IER and unmasked in IMR
etc. If written as part of a 16-bit or 32-bit write, only one
interrupt is generated in common.
Reserved
ASLE Scratch Trigger 3 (AST3):
when IER bit 0 is enabled and IMR bit 0 is unmasked. If
written as part of a 16-bit or 32-bit write, only one
interrupt is generated in common.
ASLE Scratch Trigger 2 (AST2):
when IER bit 0 is enabled and IMR bit 0 is unmasked. If
written as part of a 16-bit or 32-bit write, only one
interrupt is generated in common.
When written, this scratch byte triggers an interrupt
When written, this scratch byte triggers an interrupt
0/2/0/PCI
F4-F7h
00000000h
32 bits
0/2/0/PCI
E4-E7h
00000000h
32 bits
RW;
RW;
Description
Description
147