AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 162
AU80610004653AAS LBMG
Manufacturer Part Number
AU80610004653AAS LBMG
Description
MPU, ATOM PROCESSOR, N450, FC-BGA8
Manufacturer
Intel
Series
ATOM - N400r
Datasheet
1.AU80610004653AAS_LBMG.pdf
(171 pages)
Specifications of AU80610004653AAS LBMG
Core Size
64bit
Cpu Speed
1.66GHz
Digital Ic Case Style
BGA
No. Of Pins
559
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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1.10.19
162
7:4
3:2
Bit
1
0
Access
RO
RO
RO
RO
DEVEN - Device Enable
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Allows for enabling/disabling of PCI devices and functions that are within the processor.
The table below the bit definitions describes the behavior of all combinations of
transactions to devices controlled by this register.
Default
Value
0011b
00b
0b
0b
RST/
PWR
Core
Core
Core
Core
Graphics Mode Select (GMS):
pre-allocated to support the Internal Graphics device in VGA
(non-linear) and Native (linear) modes. The BIOS ensures that
memory is pre-allocated only when Internal graphics is enabled.
NOTE: This register is locked and becomes Read Only when the
BIOS Requirement: BIOS must not set this field to 000 if IVD (bit
1 of this register) is 0.
Reserved
IGD VGA Disable (IVD):
Sub-Class Code within Device 2 Class Code register is 00.
IO), and the Sub- Class Code field within Device 2 function 0
Class Code register is 80.
BIOS Requirement: BIOS must not set this bit to 0 if the GMS
field (bits 6:4 of this register) pre-allocates no memory.
or fuse override (CAPID0[38] = 1) or via a register (DEVEN[3] =
0).
Reserved
D_LCK bit in the SMRAM register is set.
0: Enable. Device 2 (IGD) claims VGA memory and IO cycles, the
This field is used to select the amount of Main Memory that is
0000
Others
1: Disable. Device 2 (IGD) does not claim VGA cycles (Mem and
This bit MUST be set to 1 if Device 2 is disabled either via a fuse
0001
0011
No memory pre-allocated. Device 2 (IGD) does not
claim VGA cycles (Mem and IO), and the Sub-Class
Code field within Device 2 function 0 Class Code
register is 80.
DVMT (UMA) mode, 1 MB of memory pre-allocated for
frame buffer.
DVMT (UMA) mode, 8 MB of memory pre-allocated for
frame buffer.
Reserved
0/2/1/PCI
54-57h
00000019h
32 bits
RO;
Description
Processor Configuration Registers
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