AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 166

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AU80610004653AAS LBMG

Manufacturer Part Number
AU80610004653AAS LBMG
Description
MPU, ATOM PROCESSOR, N450, FC-BGA8
Manufacturer
Intel
Series
ATOM - N400r
Datasheet

Specifications of AU80610004653AAS LBMG

Core Size
64bit
Cpu Speed
1.66GHz
Digital Ic Case Style
BGA
No. Of Pins
559
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
1.10.24
166
15:11
8:6
2:0
Bit
10
9
5
4
3
Access
PMCAP - Mirror of Fun 0 Power Management Capabilities
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register is a Mirror of Function 0 with the same read/write attributes. The
hardware implements a single physical register common to both functions 0 and 1.
RO
RO
RO
RO
RO
RO
RO
RO
Default
Value
000b
010b
00h
0b
0b
1b
0b
0b
RST/PWR
Core
Core
Core
Core
Core
Core
Core
Core
PME Support (PMES):
This field indicates the power states in which the IGD
may assert PME#. Hardwired to 0 to indicate that the
IGD does not assert the PME# signal.
D2 Support (D2):
The D2 power management state is not supported. This
bit is hardwired to 0.
D1 Support (D1):
Hardwired to 0 to indicate that the D1 power
management state is not supported.
Reserved
Device Specific Initialization (DSI):
Hardwired to 1 to indicate that special initialization of the
IGD is required before generic class device driver is to
use it.
Reserved
PME Clock (PMECLK):
Hardwired to 0 to indicate IGD does not support PME#
generation.
Version (VER):
Hardwired to 010b to indicate that there are 4 bytes of
power management registers implemented and that this
device complies with revision 1.1 of the PCI Power
Management Interface Specification.
0/2/1/PCI
D2-D3h
0022h
16 bits
RO;
Processor Configuration Registers
Description
Datasheet

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