AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 167

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AU80610004653AAS LBMG

Manufacturer Part Number
AU80610004653AAS LBMG
Description
MPU, ATOM PROCESSOR, N450, FC-BGA8
Manufacturer
Intel
Series
ATOM - N400r
Datasheet

Specifications of AU80610004653AAS LBMG

Core Size
64bit
Cpu Speed
1.66GHz
Digital Ic Case Style
BGA
No. Of Pins
559
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Processor Configuration Registers
1.10.25
Datasheet
14:13
12:9
7:2
1:0
Bit
15
8
Access
PMCS - Power Management Control/Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
RW
RO
RO
RO
RO
RO
Default
Value
00b
00h
00b
0b
0h
0b
RST/PWR
FLR, Core
Core
Core
Core
Core
Core
PME Status (PMESTS):
This bit is 0 to indicate that IGD does not support PME#
generation from D3 (cold).
Data Scale (DSCALE):
The IGD does not support data register. This bit always
returns 0 when read, write operations have no effect.
Data Select (DATASEL):
The IGD does not support data register. This bit always
returns 0 when read, write operations have no effect.
PME Enable (PME_EN):
This bit is 0 to indicate that PME# assertion from D3
(cold) is disabled.
Reserved
Power State (PWRSTAT):
This field indicates the current power state of the IGD
and can be used to set the IGD into a new power state. If
software attempts to write an unsupported state to this
field, write operation must complete normally on the
bus, but the data is discarded and no state change
occurs. On a transition from D3 to D0 the graphics
controller is optionally reset to initial values. Behavior of
the graphics controller in supported states is detailed in
the power management section of the BIOS
specification.
Bits[1:0] Power state
00:D0Default
01:D1Not Supported
10:D2Not Supported
11:D3
0/2/1/PCI
D4-D5h
0000h
16 bits
RO; RW;
Description
167

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