AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 168

• Manufacturer Part Number: AU80610004653AAS LBMG
• Description: MPU, ATOM PROCESSOR, N450, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - N400r

Specifications of AU80610004653AAS LBMG

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.10.26
1.10.27
168
31:24
23:16
15:8
7:1
Bit
Bit
0
Access
Access
SWSMI - Mirror of Func0 Software SMI
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
As long as there is the potential that DVO port legacy drivers exist which expect this
register at this address, Dev#2F0address E0h-E1h must be reserved for this register.
ASLE - Mirror of Dev2 Func0 System Display Event
Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
RO
RO
RO
RO
RO
Default
Default
Value
Value
00h
00h
00h
00h
0b
RST/PWR
RST/PWR
Core
Core
Core
Core
Core
Software Scratch Bits (SWSB):
Software Flag (SWF):
as return result.
processor Software SMI Event (GSSMIE):
write a “0” to clear this bit.
ASLE Scratch Trigger 3 (AST3):
when IER bit 0 is enabled and IMR bit 0 is unmasked. If
written as part of a 16-bit or 32-bit write, only one
interrupt is generated in common.
ASLE Scratch Trigger 2 (AST2):
when IER bit 0 is enabled and IMR bit 0 is unmasked. If
written as part of a 16-bit or 32-bit write, only one
interrupt is generated in common.
Used to indicate caller and SMI function desired, as well
When Set this bit will trigger an SMI. Software must
When written, this scratch byte triggers an interrupt
When written, this scratch byte triggers an interrupt
0/2/1/PCI
E0-E1h
0000h
16 bits
0/2/1/PCI
E4-E7h
00000000h
32 bits
RO;
RO;
Processor Configuration Registers
Description
Description
Datasheet