AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 170
AU80610004653AAS LBMG
Manufacturer Part Number
AU80610004653AAS LBMG
Description
MPU, ATOM PROCESSOR, N450, FC-BGA8
Manufacturer
Intel
Series
ATOM - N400r
Datasheet
1.AU80610004653AAS_LBMG.pdf
(171 pages)
Specifications of AU80610004653AAS LBMG
Core Size
64bit
Cpu Speed
1.66GHz
Digital Ic Case Style
BGA
No. Of Pins
559
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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1.11
1.11.1
170
Device 2 IO
Index - MMIO Address Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
MMIO_INDEX: A 32 bit IO write to this port loads the offset of the MMIO register or
offset into the GTT that needs to be accessed. An IO Read returns the current value of
this register. An 8/16 bit IO write to this register is completed by the CPU UNCORE but
does not update this register.
This mechanism to access internal graphics MMIO registers must not be used to access
VGA IO registers which are mapped through the MMIO space. VGA registers must be
accessed directly through the dedicated VGA IO ports.
MMIO Address Register
MMIO Data Register
31:2
1:0
Bit
Register Name
Access
RW
RW
00000000h
Default
Register
Symbol
Value
Index
00b
Data
RST/PWR
Register
0/2/0/PCI IO
0-3h
00000000h
32 bits
RW;
Start
Core
Core
0
4
Register
Register/GTT Offset (REGGTTO):
This field selects any one of the DWORD
registers within the MMIO register space
of Device #2 if the target is MMIO
Registers.
This field selects a GTT offset if the target
is the GTT.
Target (TARG):
00: MMIO Registers
01: GTT
1X: Reserved
End
3
7
Processor Configuration Registers
00000000h
00000000h
Default Value
Description
Access
RW;
RW;
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