AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 22

• Manufacturer Part Number: AU80610004653AAS LBMG
• Description: MPU, ATOM PROCESSOR, N450, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - N400r

Specifications of AU80610004653AAS LBMG

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.2.3.2
1.2.3.3
1.2.4
22
Note:
to FECF_FFFFh range so that one MTRR can be programmed to 64 KB for the Local and
I/O APICs. The I/O APIC(s) usually reside in the ICH portion of the chip set or as a
stand-alone component(s).
I/O APIC units will be located beginning at the default address FEC0_0000h. The first I/
O APIC will be located at FEC0_0000h. Each I/O APIC unit is located at FEC0_x000h
where x is I/O APIC unit number 0 through F(hex). This address range will normally be
mapped to DMI.
There is no provision to support an I/O APIC device on PCI Express.
HSEG (FEDA_0000h-FEDB_FFFFh)
This optional segment from FEDA_0000h to FEDB_FFFFh provides a remapping window
to SMM memory. It is sometimes called the High SMM memory space. SMM-mode CPU
accesses to the optionally enabled HSEG are remapped to 000A_0000h - 000B_FFFFh.
Non-SMM mode CPU accesses to enabled HSEG are considered invalid and are
terminated immediately on the FSB. The exceptions to this rule are Non-SMM mode
Write Back cycles which are remapped to SMM space to maintain cache coherency. PCI
Express and DMI originated cycles to enabled SMM space are not allowed. Physical
DRAM behind the HSEG transaction address is not remapped and is not accessible. All
Cacheline writes with WB attribute or implicit write backs to the HSEG range are
completed to DRAM like an SMM cycle.
High BIOS Area
The top 2 MB (FFE0_0000h -FFFF_FFFFh) of the PCI Memory Address Range is reserved
for System BIOS (High BIOS), extended BIOS for PCI devices, and the A20 alias of the
system BIOS. The CPU begins execution from the High BIOS after reset. This region is
mapped to DMI so that the upper subset of this region aliases to the 16-MB–256-KB
range. The actual address space required for the BIOS is less than 2 MB but the
minimum CPU MTRR range for this region is 2 MB so that full 2 MB must be considered.
Graphics Memory Address Ranges
The processor can be programmed to direct memory accesses to IGD when addresses
are within any of ranges specified via registers in processor’s Device 2 configuration
space.
Normally these ranges will reside above the Top-of-Low-DRAM and below High BIOS
and APIC address ranges. They normally reside above the top of memory (TOLUD) so
they do not steal any physical DRAM memory space.
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•
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The Memory Map Base register (MMADR) is used to access graphics control
registers.
The Graphics Memory Aperture Base register (GMADR) is used to access graphics
memory allocated via the graphics translation table.
The Graphics Translation Table Base register (GTTADR) is used to access the
translation table.
Processor Configuration Registers
Datasheet