AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 23

• Manufacturer Part Number: AU80610004653AAS LBMG
• Description: MPU, ATOM PROCESSOR, N450, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - N400r

Specifications of AU80610004653AAS LBMG

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Processor Configuration Registers
1.2.4.1
1.2.4.2
Datasheet
GMADR is a Prefetchable range in order to apply USWC attribute (from the processor
point of view) to that range. The USWC attribute is used by the processor for write
combining.
Graphics Register Ranges
This section provides a high-level register map (register groupings per function) for the
integrated graphics. The memory and I/O maps for the graphics registers are shown in
Figure
can be accessed via standard VGA I/O locations as well as via memory-mapped
locations. In addition, the memory map contains allocation ranges for various
functions. The memory space address listed for each register is an offset from the base
memory address programmed into the MMADR register (PCI configuration offset 14h).
The same memory space can be accessed via dword accesses to I/OBAR. Through the
IOBAR, I/O registers MMIO_index and MMIO_data are written.
VGA and Extended VGA Control Registers (00000h-00FFFh)
These registers are located in both I/O space and memory space. The VGA and
Extended VGA registers contain the following register sets: General Control/Status,
Sequencer (SRxx), Graphics Controller (GRxx), Attribute Controller (ARxx), VGA Color
Palette, and CRT Controller (CRxx) registers.
Instruction, Memory, and Interrupt Control Registers (01000h-02FFFh)
The Instruction and Interrupt Control registers are located in main memory space and
contain the types of registers listed in the following sections.
I/O Mapped Access to Device 2 MMIO Space
If Device 2 is enabled, and Function 0 within Device 2 is enabled, then IGD registers
can be accessed using the IOBAR.
MMIO_Index: MMIO_INDEX is a 32-bit register. An I/O write to this port loads the
address of the MMIO register that needs to be accessed. I/O Reads returns the current
value of this register.
MMIO_Data: MMIO_DATA is a 32-bit register. An I/O write to this port is re-directed to
the MMIO register pointed to by the MMIO-index register. An I/O read to this port is re-
directed to the MMIO register pointed to by the MMIO-index register.
1-5, except PCI Configuration registers. The VGA and Extended VGA registers
23