AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 26

• Manufacturer Part Number: AU80610004653AAS LBMG
• Description: MPU, ATOM PROCESSOR, N450, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - N400r

Specifications of AU80610004653AAS LBMG

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.2.5.2
1.2.5.3
1.2.5.4
26
Table 1-5. SMM Space Definition Summary
Table 1-6. SMM Space Table
SMM Space restrictions
If any of the following conditions are violated, the results of SMM accesses are
unpredictable and may cause the system to hang:
SMM Space Combinations
When High SMM is enabled (G_SMRAME=1 and H_SMRAM_EN=1) the Compatible SMM
space is effectively disabled. CPU originated accesses to the Compatible SMM space are
forwarded to PCI Express if VGAEN=1 (also depends on MDAP), otherwise they are
forwarded to the DMI. PCI Express and DMI originated accesses are never allowed to
access SMM space.
SMM Control Combinations
The G_SMRAME bit provides a global enable for all SMM memory. The D_OPEN bit
allows software to write to the SMM ranges without being in SMM mode. BIOS software
can use this bit to initialize SMM code at power-up. The D_LCK bit limits the SMM range
Compatible (C)
High (H)
TSEG (T)
•
•
•
•
•
Global Enable
G_SMRAME
The Compatible SMM space must not be set-up as cacheable.
High or TSEG SMM transaction address space must not overlap address space
assigned to system DRAM, or to any “PCI” devices (including DMI, PCI Express, and
graphics devices). This is a BIOS responsibility.
Both D_OPEN and D_CLOSE must not be set to 1 at the same time.
When TSEG SMM space is enabled, the TSEG space must not be reported to the
OS as available DRAM. This is a BIOS responsibility.
Any address translated through the GMADR must not target DRAM from A_0000-
F_FFFF.
SMM Space Enabled
0
1
1
1
1
H_SMRAM_EN
High Enable
X
0
0
1
1
000A_0000h to 000B_FFFFh
FEDA_0000h to FEDB_FFFFh
(TOLUD-STOLEN-TSEG) to
TOLUD-STOLEN
Transaction Address Space
TSEG Enable
TSEG_EN
X
0
1
0
1
Compatible
(C) Range
Disabled
Disabled
Disable
Processor Configuration Registers
Enable
Enable
000A_0000h to 000B_FFFFh
000A_0000h to 000B_FFFFh
(TOLUD-STOLEN-TSEG) to
TOLUD-STOLEN
DRAM Space (DRAM)
High (H)
Disable
Disable
Range
Disable
Enable
Enable
TSEG (T)
Disable
Disable
Disable
Datasheet
Range
Enable
Enable