AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 27

• Manufacturer Part Number: AU80610004653AAS LBMG
• Description: MPU, ATOM PROCESSOR, N450, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - N400r

Specifications of AU80610004653AAS LBMG

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Processor Configuration Registers
1.2.5.5
1.2.5.6
1.2.5.7
Datasheet
Table 1-7. SMM Control Table
access to only SMM mode accesses. The D_CLS bit causes SMM data accesses to be
forwarded to the DMI or PCI Express. The SMM software can use this bit to write to
video memory while running SMM code out of DRAM.
SMM Space Decode and Transaction Handling
Only the CPU is allowed to access SMM space. DMI originated transactions are not
allowed to SMM space.
CPU WB Transaction to an Enabled SMM Address Space
CPU Writeback transactions (REQ[1]# = 0) to enabled SMM address space must be
written to the associated SMM DRAM even though D_OPEN=0 and the transaction is
not performed in SMM mode. This ensures SMM space cache coherency when cacheable
extended SMM space is used.
SMM Access through GTT TLB
Accesses through GTT TLB address translation to enabled SMM DRAM space are not
allowed. Writes will be routed to Memory address 000C_0000h with byte enables
deasserted and reads will be routed to Memory address 000C_0000h. If a GTT TLB
translated address hits enabled SMM DRAM space, an error is recorded in the
PGTBL_ER register.
DMI Interface originated accesses are never allowed to access SMM space directly or
through the GTT TLB address translation. If a GTT TLB translated address hits enabled
SMM DRAM space, an error is recorded in the PGTBL_ER register.
DMI Interface write accesses through GMADR range will be snooped. Assesses to
GMADR linear range (defined via fence registers) are supported. DMI Interface tileY
and tileX writes to GMADR are not supported. If, when translated, the resulting physical
address is to enabled SMM DRAM space, the request will be remapped to address
000C_0000h with deasserted byte enables.
G_SMRAME
0
1
1
1
1
1
1
1
1
D_LCK
x
0
0
0
0
0
1
1
1
D_CLS
X
X
0
0
1
1
X
0
1
D_OPEN
x
0
0
1
0
1
x
x
x
CPU in SMM
Mode
x
0
1
x
1
x
0
1
1
SMM Code
Access
Disable
Disable
Disable
Enable
Enable
Enable
Invalid
Enable
Enable
SMM Data
Access
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Invalid
Enable
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