AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 29

• Manufacturer Part Number: AU80610004653AAS LBMG
• Description: MPU, ATOM PROCESSOR, N450, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - N400r

Specifications of AU80610004653AAS LBMG

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Processor Configuration Registers
1.2.8
1.2.8.1
1.3
Datasheet
The processor responds to I/O cycles initiated on DMI with a UR status. Upstream I/O
cycles and configuration cycles should never occur. If one does occur, the request will
route as a read to memory address 0h so a completion is naturally generated (whether
the original request was a read or write). The transaction will complete with a UR
completion status.
Memory Controller Decode Rules and Cross-Bridge
Address Mapping
VGAA = 000A_0000 – 000A_FFFF
MDA = 000B_0000 – 000B_7FFF
VGAB = 000B_8000 – 000B_FFFF
MAINMEM = 0100_0000 to TOLUD
Legacy VGA and I/O Range Decode Rules
The legacy 128-KB VGA memory range 000A_0000h-000B_FFFFh can be mapped to
IGD (Device 2), and/or to the DMI depending on the programming of the VGA steering
bits. Priority for VGA mapping is constant in that the GMCH always decodes internally
mapped devices first. Internal to the GMCH, decode precedence is always given to IGD.
The GMCH always positively decodes internally mapped devices, namely the IGD.
Subsequent decoding of regions mapped to the DMI depends on the Legacy VGA
configurations bits (VGA Enable and MDAP).
The processor processor internal registers (I/O Mapped Configuration and PCI Express
Extended Configuration registers) are accessible by the Host CPU. The registers that
reside within the lower 256 bytes of each device can be accessed as Byte, Word (16-
bit), or Dword (32-bit) quantities, with the exception of CONFIG_ADDRESS which can
only be accessed as a Dword. All multi-byte numeric fields use “little-Indian” ordering
(i.e., lower addresses contain the least significant parts of the field). Registers which
reside in bytes 256 through 4095 of each device may only be accessed using memory
mapped transactions in Dword (32-bit) quantities.
Some of the processor registers described in this section contain reserved bits. These
bits are labeled “Reserved”. Software must deal correctly with fields that are reserved.
On reads, software must use appropriate masks to extract the defined bits and not rely
on reserved bits being any particular value. On writes, software must ensure that the
values of reserved bit positions are preserved. That is, the values of reserved bit
positions must first be read, merged with the new values for other bit positions and
then written back. Note the software does not need to perform read, merge, write
operation for the configuration address register.
Processor Register Introduction
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