AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 30

• Manufacturer Part Number: AU80610004653AAS LBMG
• Description: MPU, ATOM PROCESSOR, N450, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - N400r

Specifications of AU80610004653AAS LBMG

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.4
1.5
30
Vendor
Identification
Device
Identification
PCI Command
Table 1-8. Device 0 Function 0 Register Summary (Sheet 1 of 3)
Register Name
In addition to reserved bits within a register, the processor contains address locations
in the configuration space of the Host Bridge entity that are marked either “Reserved”
or “Intel Reserved”. The CPU responds to accesses to “Reserved” address locations by
completing the host cycle. When a “Reserved” register location is read, a zero value is
returned. (“Reserved” registers can be 8-, 16-, or 32-bit in size). Writes to “Reserved”
registers have no effect on the CPU. Registers that are marked as “Intel Reserved”
must not be modified by system software. Writes to “Intel Reserved” registers may
cause system failure. Reads to “Intel Reserved” registers may return a non-zero value.
Upon a Full Reset, the processor sets all of its internal configuration registers to
predetermined default states. Some register values at reset are determined by external
strapping options, or the states of polysilicon fuses. The default state represents the
minimum functionality feature set required to successfully bring up the system. Hence,
it does not represent the optimal system configuration. It is the responsibility of the
system initialization software (usually BIOS) to properly determine the DRAM
configurations, operating parameters and optional system features that are applicable,
and to program the processor registers accordingly.
I/O Mapped Registers
The processor contains two registers that reside in the processor I/O address space -
the Configuration Address (CONFIG_ADDRESS) Register and the Configuration Data
(CONFIG_DATA) Register. The Configuration Address Register enables/disables the
configuration space and determines what portion of configuration space is visible
through the Configuration Data window.
PCI Device 0
The processor/DMI controller registers are in Device 0 (D0), Function 0 (F0).
Address locations that are not listed are considered Intel Reserved registers locations.
Reads to Reserved registers may return non-zero values. Writes to reserved locations
may cause system failures.
All registers that are defined in the latest PCI Local Bus Specification, but are not
necessary or implemented in this component are simply not included in this document.
The reserved/unimplemented space in the PCI configuration header space is not
documented as such in this summary.
VID
DID
PCICMD
Register
Symbol
Register
Start
0
2
4
Register End
1
3
5
Processor Configuration Registers
8086h
A010h
0006h
Default Value
RO;
RO;
RO; RW;
Access
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