AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 46

• Manufacturer Part Number: AU80610004653AAS LBMG
• Description: MPU, ATOM PROCESSOR, N450, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - N400r

Specifications of AU80610004653AAS LBMG

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.5.16
46
PCIEXBAR - PCI Express Register Range Base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This is the base address for the PCI Express configuration space. This window of
addresses contains the 4KB of configuration space for each PCI Express device that can
potentially be part of the PCI Express Hierarchy associated with the CPU UNCORE.
There is not actual physical memory within this window of up to 256MB that can be
addressed. The actual length is determined by a field in this register. Each PCI Express
Hierarchy requires a PCI Express BASE register. The CPU UNCORE supports one PCI
Express hierarchy. The region reserved by this register does not alias to any PCI 2.3
compliant memory mapped space. For example MCHBAR reserves a 16KB space and
CHAPADR reserves a 4KB space both outside of PCIEXBAR space. They cannot be
overlayed on the space reserved by PCIEXBAR for devices 0 and 7 respectively.
On reset, this register is disabled and must be enabled by writing a 1 to the enable field
in this register. This base address shall be assigned on a boundary consistent with the
number of buses (defined by the Length field in this register), above TOLUD and still
within 64 bit addressable memory space. All other bits not decoded are read only 0.
The PCI Express Base Address cannot be less than the maximum address written to the
Top of physical memory register (TOLUD). Software must guarantee that these ranges
do not overlap with known ranges located above TOLUD. Software must ensure that the
sum of Length of enhanced configuration region + TOLUD + (other known ranges
2:1
Bit
3
0
Access
RW-L
RO
RO
Default
Value
00b
1b
1b
0/0/0/PCI
60-67h
00000000E0000000h
RW/L; RO; RW/L/K
64 bits
RST/
PWR
Core
Core
Core
Internal Graphics Engine Function 0
(D2F0EN):
0: Bus 0 Device 2 Function 0 is disabled
and hidden
1: Bus 0 Device 2 Function 0 is enabled
and visible
If this processor does not have internal
graphics capability (CAPID0[46] = 1) then
Device 2 Function 0 is disabled and
hidden independent of the state of this
bit.
Reserved
Host Bridge (D0EN):
Bus 0 Device 0 Function 0 may not be
disabled and is therefore hardwired to 1.
Processor Configuration Registers
Description
Datasheet