AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 48

• Manufacturer Part Number: AU80610004653AAS LBMG
• Description: MPU, ATOM PROCESSOR, N450, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - N400r

Specifications of AU80610004653AAS LBMG

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.5.17
48
25:3
2:1
Bit
0
Access
RW-L-K
RW-L
DMIBAR - Root Complex Register Range Base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This is the base address for the Root Complex configuration space. This window of
addresses contains the Root Complex Register set for the PCI Express Hierarchy
associated with the processor. There is no physical memory within this 4-KB window
that can be addressed. The 4-KB reserved by this register does not alias to any PCI
3.0-compliant memory mapped space. On reset, the Root Complex configuration space
is disabled and must be enabled by writing a 1 to DMIBAREN [Device 0, Offset 68h, Bit
0].
RO
000000h
Default
Value
00b
0b
RST/
PWR
Core
Core
Core
Reserved
Length (LENGTH):
This Field describes the length of this region.
Enhanced Configuration Space Region/Buses Decoded
00: 256MB (buses 0-255). Bits 31:28 are decoded in the
PCI Express Base Address Field
01: 128MB (Buses 0-127). Bits 31:27 are decoded in the
PCI Express Base Address Field.
10: 64MB (Buses 0-63). Bits 31:26 are decoded in the
PCI Express Base Address Field.
11: Reserved
PCIEXBAR Enable (PCIEXBAREN):
0: The PCIEXBAR register is disabled. Memory read and
write transactions proceed as if there were no PCIEXBAR
register. PCIEXBAR bits 35:26 are R/W with no
functionality behind them.
1: The PCIEXBAR register is enabled. Memory read and
write transactions whose address bits 35:26 match
PCIEXBAR will be translated to configuration reads and
writes within the processor UNCORE. These Translated
cycles are routed as shown in the table above.
0/0/0/PCI
68-6Fh
0000000000000000h
RW-L; RO
64 bits
Processor Configuration Registers
Description
Datasheet