AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 6
AU80610004653AAS LBMG
Manufacturer Part Number
AU80610004653AAS LBMG
Description
MPU, ATOM PROCESSOR, N450, FC-BGA8
Manufacturer
Intel
Series
ATOM - N400r
Datasheet
1.AU80610004653AAS_LBMG.pdf
(171 pages)
Specifications of AU80610004653AAS LBMG
Core Size
64bit
Cpu Speed
1.66GHz
Digital Ic Case Style
BGA
No. Of Pins
559
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Figures
6
1.11
1-1
1-2
1-3
1-4
1-5
1.10.7 CLS - Cache Line Size............................................................................ 155
1.10.8 MLT2 - Master Latency Timer ................................................................. 156
1.10.9 HDR2 - Header Type ............................................................................. 156
1.10.10MMADR - Memory Mapped Range Address................................................ 157
1.10.11SVID2 - Subsystem Vendor Identification................................................. 157
1.10.12SID2 - Subsystem Identification ............................................................. 158
1.10.13ROMADR - Video BIOS ROM Base Address................................................ 158
1.10.14CAPPOINT - Capabilities Pointer .............................................................. 159
1.10.15MINGNT - Minimum Grant ...................................................................... 159
1.10.16MAXLAT - Maximum Latency .................................................................. 159
1.10.17CAPID0 - Mirror of Device 0 Capability Identifier ....................................... 160
1.10.18MGGC - Mirror of Dev 0 processor Graphics Control Register....................... 161
1.10.19DEVEN - Device Enable.......................................................................... 162
1.10.20SSRW - Mirror of Fun 0 Software Scratch Read Write................................. 164
1.10.21BSM - Mirror of Func0 Base of Stolen Memory .......................................... 164
1.10.22HSRW - Mirror of Dev2 Func0 Hardware Scratch Read Write ....................... 165
1.10.23PMCAPID - Mirror of Fun 0 Power Management Capabilities ID .................... 165
1.10.24PMCAP - Mirror of Fun 0 Power Management Capabilities............................ 166
1.10.25PMCS - Power Management Control/Status............................................... 167
1.10.26SWSMI - Mirror of Func0 Software SMI .................................................... 168
1.10.27ASLE - Mirror of Dev2 Func0 System Display Event Register ....................... 168
1.10.28ASLS - ASL Storage .............................................................................. 169
Device 2 IO..................................................................................................... 170
1.11.1 Index - MMIO Address Register............................................................... 170
1.11.2 Data - MMIO Data Register .................................................................... 171
System Address Ranges ..........................................................................14
DOS Legacy Address Range .....................................................................15
Main Memory Address Range....................................................................18
PCI Memory Address Range .....................................................................21
Graphics Register Memory and I/O Map .....................................................24
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