AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 61

• Manufacturer Part Number: AU80610004653AAS LBMG
• Description: MPU, ATOM PROCESSOR, N450, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - N400r

Specifications of AU80610004653AAS LBMG

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Processor Configuration Registers
1.5.30
Datasheet
15:10
2:1
9:0
Bit
Bit
0
Access
Access
RW-L
RW-L
RW-L
TOM - Top of Memory
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This Register contains the size of physical memory. BIOS determines the memory size
reported to the OS using this Register.
RO
Default
Default
Value
Value
001h
00b
00h
0b
RST/
RST/
PWR
PWR
Core
Core
Core
Core
TSEG Size (TSEG_SZ):
Selects the size of the TSEG memory block if enabled.
Memory from the top of DRAM space is partitioned away
so that it may only be accessed by the processor interface
and only then when the SMM bit is set in the request
packet. Non-SMM accesses to this memory region are sent
to DMI when the TSEG memory block is enabled.
00:1MB Tseg. (TOLUD - GTT Graphics Memory Size -
Graphics Stolen Memory Size - 1M to (TOLUD - GTT
Graphics Memory Size - Graphics Stolen Memory Size).
01: 2 MB Tseg (TOLUD - GTT Graphics Memory Size -
Graphics Stolen Memory Size - 2M to (TOLUD - GTT
Graphics Memory Size - Graphics Stolen Memory Size).
10: 8 MB Tseg (TOLUD - GTT Graphics Memory Size -
Graphics Stolen Memory Size - 8M) to (TOLUD - GTT
Graphics Memory Size - Graphics Stolen Memory Size).
11: Reserved.
Once D_LCK has been set, these bits becomes read only.
TSEG Enable (T_EN):
Enabling of SMRAM memory for Extended SMRAM space
only. When G_SMRAME = 1 and TSEG_EN = 1, the TSEG is
enabled to appear in the appropriate physical address
space.
NOTE: Once D_LCK is set, this bit becomes read only.
Reserved
Top of Memory (TOM):
This register reflects the total amount of populated
physical memory. This is NOT necessarily the highest main
memory address (holes may exist in main memory
address map due to addresses allocated for memory
mapped IO). These bits correspond to address bits 35:26
(64MB granularity). Bits 25:0 are assumed to be 0.
0/0/0/PCI
A0-A1h
0001h
16 bits
RO; RW-L;
Description
Description
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