AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 66

• Manufacturer Part Number: AU80610004653AAS LBMG
• Description: MPU, ATOM PROCESSOR, N450, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - N400r

Specifications of AU80610004653AAS LBMG

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.5.36
66
15:4
3:0
Bit
Access
RW-L
ERRSTS - Error Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register is used to report various error conditions via the SERR DMI messaging
mechanism. An SERR DMI message is generated on a zero to one transition of any of
these flags (if enabled by the ERRCMD and PCICMD registers).
These bits are set regardless of whether or not the SERR is enabled and generated.
After the error processing is complete, the error logging mechanism can be unlocked by
clearing the appropriate status bit by software writing a '1' to it.
RO
Default
Value
0000b
001h
RST/PWR
Core
Core
Top of Low Usable DRAM (TOLUD):
This register contains bits 31 to 20 of an address one byte
above the maximum DRAM memory below 4G that is
usable by the operating system. Address bits 31 down to
20 programmed to 01h implies a minimum memory size
of 1MBs. Configuration software must set this value to the
smaller of the following 2 choices: maximum amount
memory in the system minus ME stolen memory plus one
byte or the minimum address allocated for PCI memory.
Address bits 19:0 are assumed to be 0_0000h for the
purposes of address comparison. The Host interface
positively decodes an address towards DRAM if the
incoming address is less than the value programmed in
this register.
NOTE: The Top of Low Usable DRAM is the lowest address
This register must be 64MB aligned when reclaim is
enabled.
Reserved
0/0/0/PCI
C8-C9h
0000h
16 bits
RO; RWC/S;
above both Graphics Stolen memory and Tseg.
BIOS determines the base of Graphics Stolen
Memory by subtracting the Graphics Stolen
Memory Size from TOLUD and further decrements
by Tseg size to determine base of Tseg. All the Bits
in this register are locked in MSLOCK.
Processor Configuration Registers
Description
Datasheet