AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 69
AU80610004653AAS LBMG
Manufacturer Part Number
AU80610004653AAS LBMG
Description
MPU, ATOM PROCESSOR, N450, FC-BGA8
Manufacturer
Intel
Series
ATOM - N400r
Datasheet
1.AU80610004653AAS_LBMG.pdf
(171 pages)
Specifications of AU80610004653AAS LBMG
Core Size
64bit
Cpu Speed
1.66GHz
Digital Ic Case Style
BGA
No. Of Pins
559
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Processor Configuration Registers
1.5.38
Datasheet
Note:
SMICMD - SMI Command
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
error flag is set in the ERRSTS register, it can generate an SERR, SMI, or SCI DMI
special cycle when enabled in the ERRCMD, SMICMD, or SCICMD registers,
respectively.
One and only one message type can be enabled.
This register enables various errors to generate an SMI DMI special cycle. When an
15:12
10:2
6:2
Bit
Bit
11
7
1
0
1
0
Access
Access
RW
RW
RO
RO
RO
RO
RO
RO
RO
Default
Default
Value
Value
000h
00h
0b
0b
0b
0h
0b
0b
0b
0/0/0/PCI
CC-CDh
0000h
16 bits
RO; RW;
RST/
RST/
PWR
PWR
Core
Core
Core
Core
Core
Core
Core
Core
Core
SERR on DRAM Throttle Condition
(DTCERR):
1: The processor generates a DMI SERR
special cycle when a DRAM Read or Write
Throttle condition occurs.
0: Reporting of this condition via SERR
messaging is disabled.
Reserved
Reserved
Reserved
Reserved
SMI on processor Thermal Sensor
Trip (TSTSMI):
1: A SMI DMI special cycle is generated
by processor when the thermal sensor
trip requires an SMI. A thermal sensor
trip point cannot generate more than one
special cycle.
0: Reporting of this condition via SMI
messaging is disabled.
Reserved
Reserved
Reserved
Description
Description
69
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