AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 78

• Manufacturer Part Number: AU80610004653AAS LBMG
• Description: MPU, ATOM PROCESSOR, N450, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - N400r

Specifications of AU80610004653AAS LBMG

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.6.5
1.6.6
78
Note:
15:10
9:0
Bit
Access
C0DRB3 - Channel 0 DRAM Rank Boundary Address 3
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
See C0DRB0
C0DRA01 - Channel 0 DRAM Rank 0,1 Attribute
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
The DRAM Rank Attribute Registers define the page sizes/number of banks to be used
when accessing different ranks. These registers should be left with their default value
(all zeros) for any rank that is unpopulated, as determined by the corresponding
CxDRB registers. Each byte of information in the DRA registers describes the page size
of a pair of ranks. Channel and rank map:
DRA[6:0] = "00" means cfg0, DRA[6:0] =”01” means cfg1.... DRA[6:0] = “09” means
cfg9 and so on. DRA[7] indicates whether it's an 8 bank config or not. DRA[7] = 0
means 4 bank, DRA[7] = 1 means 8 bank.
RW-L
RO
•
•
Ch0 Rank0, 1:208h - 209h
Ch0 Rank2, 3:20Ah - 20Bh
000000b
Default
Value
000h
RST/
PWR
Core
Core
Reserved
Channel 0 DRAM Rank Boundary Address 3
(C0DRBA3):
This register defines the DRAM rank boundary for rank3
of Channel 0 (64 MB granularity)=(R3 + R2 + R1 + R0)
R0 = Total rank0 memory size/64 MB
R1 = Total rank1 memory size/64 MB
R2 = Total rank2 memory size/64 MB
R3 = Total rank3 memory size/64 MB
0/0/0/MCHBAR
206-207h
0000h
RO; RW-L;
16 bits
0/0/0/MCHBAR
208-209h
0000h
16 bits
RW-L;
Processor Configuration Registers
Description
Datasheet