AU80610004653AAS LBMG Intel, AU80610004653AAS LBMG Datasheet - Page 82
AU80610004653AAS LBMG
Manufacturer Part Number
AU80610004653AAS LBMG
Description
MPU, ATOM PROCESSOR, N450, FC-BGA8
Manufacturer
Intel
Series
ATOM - N400r
Datasheet
1.AU80610004653AAS_LBMG.pdf
(171 pages)
Specifications of AU80610004653AAS LBMG
Core Size
64bit
Cpu Speed
1.66GHz
Digital Ic Case Style
BGA
No. Of Pins
559
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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1.6.10
82
15:12
11:8
8:0
7:4
3:0
Bit
Bit
Access
Access
RW
C0CYCTRKWR - Channel 0 CYCTRK WR
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Channel 0 CYCTRK WR Registers.
RW
RW
RW
RW
000000000
Default
Default
Value
Value
0h
0h
0h
0h
b
RST/PWR
RST/PWR
Core
Core
Core
Core
Core
(Sheet 2 of 2)
ACT To Write Delay (C0sd_cr_act_wr):
This configuration register indicates the minimum allowed
spacing (in DRAM clocks) between the ACT and WRITE
commands to the same rank-bank.
Corresponds to tRCD_wr at DDR Spec.
Same Rank Write To Write Delayed (C0sd_cr_wrsr_wr):
This configuration register indicates the minimum allowed
spacing (in DRAM clocks) between two WRITE commands
to the same rank.
Different Rank Write to Write Delay (C0sd_cr_wrdr_wr):
This configuration register indicates the minimum allowed
spacing (in DRAM clocks) between two WRITE commands
to different ranks.
Corresponds to tWR_WR at DDR Spec.
READ To WRTE Delay (C0sd_cr_rd_wr):
This configuration register indicates the minimum allowed
spacing (in DRAM clocks) between the READ and WRITE
commands.
Corresponds to tRD_WR.
REF to ACT Delayed (C0sd_cr_rfsh_act):
This configuration register indicates the minimum
allowed spacing (in DRAM clocks) between REF and ACT
commands to the same rank.
Corresponds to tRFC at DDR Spec.
0/0/0/MCHBAR
256-257h
0000h
16 bits
RW;
Processor Configuration Registers
Description
Description
Datasheet
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